bd069a0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.450s | 961.835us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.890s | 144.113us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.010s | 205.871us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 6.370s | 10.814ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.600s | 428.356us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 15.740s | 21.241ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.220s | 7.689ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 16.140s | 13.354ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 6.590s | 19.335ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.350s | 532.416us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.950s | 238.343us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.880s | 189.618us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.750s | 110.309us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.930s | 106.262us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0.950s | 211.787us | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.930s | 110.088us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.840s | 603.752us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.350s | 532.416us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.950s | 320.143us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.000s | 199.156us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.880s | 189.618us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.940s | 116.909us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.300s | 242.048us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 1.930s | 128.121us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 19.640s | 1.292ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 52.750s | 24.845ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 1.060s | 61.018us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 52.750s | 24.845ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 1.930s | 128.121us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.780s | 32.980us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.770s | 124.907us | 1 | 1 | 100.00 |
| V1 | TOTAL | 26 | 27 | 96.30 | |||
| V2 | idcode | rv_dm_smoke | 1.450s | 961.835us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.710s | 165.344us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.960s | 119.167us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.850s | 220.621us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 4.030s | 1.818ms | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 4.281m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 10.161m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.074m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 4.633m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.110s | 143.801us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.670s | 1.876ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.820s | 232.371us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.650s | 92.747us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 19.360s | 9.199ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 0.820s | 53.690us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.950s | 120.877us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 1.330s | 796.205us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_dm_alert_test | 0.820s | 118.965us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0.930s | 25.123us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0.930s | 25.123us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 52.750s | 24.845ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.300s | 242.048us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.930s | 128.121us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 3.400s | 412.218us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 52.750s | 24.845ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.300s | 242.048us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.930s | 128.121us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 3.400s | 412.218us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 13 | 19 | 68.42 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.320s | 708.740us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 6.920s | 2.735ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 6.920s | 2.735ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.670s | 1.876ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.840s | 51.215us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.670s | 1.876ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 0.840s | 51.215us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 1.450s | 961.835us | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 0.840s | 121.595us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.890s | 302.048us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.890s | 302.048us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 0.840s | 121.595us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.060s | 43.077us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 0.810s | 14.719us | 1 | 1 | 100.00 | |
| TOTAL | 45 | 53 | 84.91 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.98126257607331281234310829499019225705572084218122503140382768779231679571317
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.91129728596580653353709064511207578423743640098147782585666129797908436184175
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.30449941419926911700909970677409024775132590737836515924659032463429532476685
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.45640885726683719899532406197542610768161736199608198149977881667270888652495
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6730) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.28372398572184165805546500342400998223765565989715455324387580948251197529534
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 53690224 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6730) { a_addr: 'hab2307dc a_data: 'h5c41bf61 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h19223 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 53690224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6810) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.19058690674499582795086589686801342295856540261622130686144275180517552514804
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43076920 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6810) { a_addr: 'hdd70d35c a_data: 'hc84eed52 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h51 a_opcode: 'h4 a_user: 'h1b34f d_param: 'h0 d_source: 'h51 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 43076920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6366) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.68532992057130931536373866057633086971152747310824842127963537005473132149442
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 25123457 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6366) { a_addr: 'h75419418 a_data: 'h4a4df1b1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h73 a_opcode: 'h4 a_user: 'h18c32 d_param: 'h0 d_source: 'h73 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 25123457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6012) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.41630574130605610043266682889859883807733234464971812258304615162549983360925
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 61018437 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6012) { a_addr: 'h2fbf9588 a_data: 'h15c2afe5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8f a_opcode: 'h4 a_user: 'h1ae22 d_param: 'h0 d_source: 'h8f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 61018437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---