bd069a0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.740s | 74.645us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.840s | 37.104us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.730s | 29.579us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.530s | 39.323us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.730s | 38.810us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.840s | 44.801us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.730s | 29.579us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.730s | 38.810us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.890s | 908.194us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.330s | 689.044us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 8.900s | 8.263ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 8.900s | 8.263ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.700s | 54.760us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.620s | 14.667us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.670s | 15.012us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.170s | 198.720us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.170s | 198.720us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.840s | 37.104us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 29.579us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 38.810us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 20.600us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.840s | 37.104us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 29.579us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 38.810us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 20.600us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.770s | 529.460us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.970s | 73.263us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.970s | 73.263us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.440s | 665.536us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.690s | 45.351us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 3.590s | 310.282us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 15 | 19 | 78.95 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.112914923073708408631845456397583225438334766817059637035406430688357505010107
Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 665535514 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x625fbd04) == 0x1
UVM_INFO @ 665535514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.53938535987473616842913095174772659654089427718182186165913544961513535880662
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 908194363 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe6b0c904) == 0x1
UVM_INFO @ 908194363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.114568551994863140486961474153466751458542090377306462164069777227439597329399
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 45350991 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45350991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
0.rv_timer_stress_all_with_rand_reset.5895238987214313345134749600898364480946433027962331984485552856973412730471
Line 149, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 310282056 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 310282056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---