SPI_DEVICE/1R1W Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.470m	1.036s	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	70.565us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.150s	468.390us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.760s	3.628ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.390s	739.229us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.630s	114.701us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.150s	468.390us	1	1	100.00
		spi_device_csr_aliasing	10.390s	739.229us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.830s	175.254us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.370s	36.934us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.010s	65.507us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.920s	7.183us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.980s	5.790us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.170s	320.198us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.170s	320.198us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	0.800s	36.612us	1	1	100.00
		spi_device_tpm_sts_read	0.920s	300.600us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.810s	529.189us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.370s	44.172ms	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.070s	3.395ms	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.070s	3.395ms	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	1.770s	234.905us	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	1.770s	234.905us	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.770s	234.905us	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	1.770s	234.905us	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.770s	234.905us	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.780s	34.537us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.476m	51.888ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.476m	51.888ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.476m	51.888ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	29.550s	3.823ms	1	1	100.00
		spi_device_read_buffer_direct	8.420s	2.349ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.476m	51.888ms	1	1	100.00
		spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.431m	163.546ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.990s	2.088ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.990s	2.088ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.470m	1.036s	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	55.490s	6.018ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.240s	235.086us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.010s	39.573us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.840s	38.121us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.740s	3.699ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.740s	3.699ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	70.565us	1	1	100.00
		spi_device_csr_rw	2.150s	468.390us	1	1	100.00
		spi_device_csr_aliasing	10.390s	739.229us	1	1	100.00
		spi_device_same_csr_outstanding	2.290s	81.729us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	70.565us	1	1	100.00
		spi_device_csr_rw	2.150s	468.390us	1	1	100.00
		spi_device_csr_aliasing	10.390s	739.229us	1	1	100.00
		spi_device_same_csr_outstanding	2.290s	81.729us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.100s	52.401us	1	1	100.00
		spi_device_tl_intg_err	9.600s	2.495ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.600s	2.495ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.577m	87.954ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.35575090493712851156048862301291717254744129287364486088874294130482674228895
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4349144 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[95])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4349144 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4349144 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[991])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.17064890397894521675297890396381636630208076854190435184234412441700209290984
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3454597 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9b786f [100110110111100001101111] vs 0x0 [0])
        UVM_ERROR @   3515597 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5fb17d [10111111011000101111101] vs 0x0 [0])
        UVM_ERROR @   3597597 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xab9fc [10101011100111111100] vs 0x0 [0])
        UVM_ERROR @   3624597 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xec7f19 [111011000111111100011001] vs 0x0 [0])
        UVM_ERROR @   3650597 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x92ccd0 [100100101100110011010000] vs 0x0 [0])