SPI_DEVICE/2P Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	40.480s	3.710ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.850s	22.725us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.150s	40.972us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.430s	371.070us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	13.610s	5.979ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.500s	81.781us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.150s	40.972us	1	1	100.00
		spi_device_csr_aliasing	13.610s	5.979ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.950s	12.872us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.050s	157.501us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.870s	19.939us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.970s	28.289us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	41.269us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.650s	178.427us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.650s	178.427us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.440s	10.950ms	1	1	100.00
		spi_device_tpm_sts_read	0.940s	89.923us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	11.310s	17.053ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	10.580s	8.587ms	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.570s	1.630ms	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.570s	1.630ms	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.250s	418.232us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.250s	418.232us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.250s	418.232us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.250s	418.232us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.250s	418.232us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.760s	128.368us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.570s	90.807us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.570s	90.807us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.570s	90.807us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.140s	483.462us	1	1	100.00
		spi_device_read_buffer_direct	5.560s	1.946ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.570s	90.807us	1	1	100.00
		spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.121m	8.255ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.890s	782.323us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.890s	782.323us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	40.480s	3.710ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	45.910s	25.887ms	1	1	100.00
V2	stress_all	spi_device_stress_all	52.260s	9.706ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.940s	81.535us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	24.490us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.240s	320.024us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.240s	320.024us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.850s	22.725us	1	1	100.00
		spi_device_csr_rw	1.150s	40.972us	1	1	100.00
		spi_device_csr_aliasing	13.610s	5.979ms	1	1	100.00
		spi_device_same_csr_outstanding	3.180s	663.752us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.850s	22.725us	1	1	100.00
		spi_device_csr_rw	1.150s	40.972us	1	1	100.00
		spi_device_csr_aliasing	13.610s	5.979ms	1	1	100.00
		spi_device_same_csr_outstanding	3.180s	663.752us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.040s	329.491us	1	1	100.00
		spi_device_tl_intg_err	5.820s	281.780us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.820s	281.780us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.058m	249.058ms	1	1	100.00
		TOTAL			33	33	100.00