SRAM_CTRL/MAIN Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 7.370s 523.767us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.840s 24.253us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 0.870s 17.954us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.400s 78.181us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.870s 56.337us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.360s 755.585us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.870s 17.954us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 56.337us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 2.231m 76.898ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.938m 11.121ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 1.387m 4.149ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.836m 4.737ms 1 1 100.00
V2 bijection sram_ctrl_bijection 15.399m 55.381ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 9.775m 14.416ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 57.340s 58.496ms 1 1 100.00
V2 executable sram_ctrl_executable 4.562m 82.789ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 12.820s 567.574us 1 1 100.00
sram_ctrl_partial_access_b2b 4.128m 6.187ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 58.540s 3.177ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 14.460s 5.456ms 1 1 100.00
sram_ctrl_throughput_w_readback 58.790s 1.862ms 1 1 100.00
V2 regwen sram_ctrl_regwen 8.053m 76.161ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.230s 360.522us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 45.782m 33.599ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 0.900s 60.400us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.910s 165.849us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.910s 165.849us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.840s 24.253us 1 1 100.00
sram_ctrl_csr_rw 0.870s 17.954us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 56.337us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.080s 44.403us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.840s 24.253us 1 1 100.00
sram_ctrl_csr_rw 0.870s 17.954us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 56.337us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.080s 44.403us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 16.080s 3.705ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
sram_ctrl_tl_intg_err 1.580s 175.019us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 1.580s 175.019us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 8.053m 76.161ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 8.053m 76.161ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.870s 17.954us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 4.562m 82.789ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 4.562m 82.789ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 4.562m 82.789ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 57.340s 58.496ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 3.570s 4.142ms 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 16.080s 3.705ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 3.830s 685.446us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 7.370s 523.767us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 7.370s 523.767us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 4.562m 82.789ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 57.340s 58.496ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 7.370s 523.767us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.740s 1.932us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 40.940s 2.214ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets