SRAM_CTRL/RET Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.950s	437.542us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	16.281us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	21.537us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.470s	156.324us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	12.251us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.740s	139.184us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	21.537us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	12.251us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.960s	1.383ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.510s	423.180us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.992m	5.933ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.637m	3.858ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	46.490s	12.127ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.282m	13.884ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.660s	2.479ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.626m	31.348ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.460s	1.162ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.830m	128.078ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.050s	532.733us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	13.990s	506.901us	1	1	100.00
		sram_ctrl_throughput_w_readback	12.660s	335.270us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.454m	6.531ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s	75.366us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	14.832m	26.447ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.680s	18.108us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.670s	259.782us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.670s	259.782us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	16.281us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	21.537us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	12.251us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.780s	247.896us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	16.281us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	21.537us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	12.251us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.780s	247.896us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.420s	209.428us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
		sram_ctrl_tl_intg_err	1.420s	250.561us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.420s	250.561us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.454m	6.531ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.454m	6.531ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	21.537us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.626m	31.348ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.626m	31.348ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.626m	31.348ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.660s	2.479ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.930s	28.607us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.420s	209.428us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.890s	28.976us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.950s	437.542us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.950s	437.542us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.626m	31.348ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.660s	2.479ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.950s	437.542us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.660s	5.692us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.460s	519.080us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.91522381230863583190261695727953825811129680884197534821862306005596056092653
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  28606897 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  28606897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.4521820610144771941437167314153960962141028107160565222499741767225238744704
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4853597ps failed at 4853597ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 4864014ps failed at 4864014ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'