SYSRST_CTRL Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: `bd069a0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.620s	2.116ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.580s	2.474ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.210s	2.423ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.750s	2.291ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	8.090s	4.014ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.790s	2.039ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.239m	71.627ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	5.220s	2.707ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.220s	2.180ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.790s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.220s	2.707ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	2.106m	66.302ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	28.360s	30.338ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.380s	3.648ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	1.820s	2.655ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	1.780s	2.522ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.370s	2.150ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	9.980s	4.443ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	4.810s	2.611ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.520s	2.421ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	35.380s	37.211ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	19.880s	11.109ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.340s	2.015ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.800s	2.042ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.640s	2.065ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.640s	2.065ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	8.090s	4.014ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.790s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.220s	2.707ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.410s	4.949ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	8.090s	4.014ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.790s	2.039ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.220s	2.707ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.410s	4.949ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	42.210s	22.011ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	45.250s	22.248ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	45.250s	22.248ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.320s	16.668ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

0.sysrst_ctrl_ultra_low_pwr.45871470034694279666758281349780298077487127626240946463183597583244640299540
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2408976198 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 2421476198 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2421476198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---