UART Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: bd069a0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.190s	465.755us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.680s	47.309us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.620s	19.025us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.900s	1.255ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	191.039us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.830s	24.794us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	19.025us	1	1	100.00
		uart_csr_aliasing	0.780s	191.039us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	16.050s	35.735ms	1	1	100.00
V2	parity	uart_smoke	1.190s	465.755us	1	1	100.00
		uart_tx_rx	16.050s	35.735ms	1	1	100.00
V2	parity_error	uart_intr	10.070s	14.229ms	1	1	100.00
		uart_rx_parity_err	2.250s	5.306ms	1	1	100.00
V2	watermark	uart_tx_rx	16.050s	35.735ms	1	1	100.00
		uart_intr	10.070s	14.229ms	1	1	100.00
V2	fifo_full	uart_fifo_full	4.678m	152.231ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.447m	74.417ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	21.840s	81.212ms	1	1	100.00
V2	rx_frame_err	uart_intr	10.070s	14.229ms	1	1	100.00
V2	rx_break_err	uart_intr	10.070s	14.229ms	1	1	100.00
V2	rx_timeout	uart_intr	10.070s	14.229ms	1	1	100.00
V2	perf	uart_perf	1.262m	4.782ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.270s	2.319ms	1	1	100.00
V2	line_loopback	uart_loopback	6.270s	2.319ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	10.890s	25.513ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.930s	4.473ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	11.850s	7.043ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.310s	4.117ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.872m	141.662ms	1	1	100.00
V2	stress_all	uart_stress_all	21.356m	257.692ms	1	1	100.00
V2	alert_test	uart_alert_test	0.780s	12.414us	1	1	100.00
V2	intr_test	uart_intr_test	0.670s	15.814us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.150s	28.927us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.150s	28.927us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.680s	47.309us	1	1	100.00
		uart_csr_rw	0.620s	19.025us	1	1	100.00
		uart_csr_aliasing	0.780s	191.039us	1	1	100.00
		uart_same_csr_outstanding	0.660s	93.105us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.680s	47.309us	1	1	100.00
		uart_csr_rw	0.620s	19.025us	1	1	100.00
		uart_csr_aliasing	0.780s	191.039us	1	1	100.00
		uart_same_csr_outstanding	0.660s	93.105us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.990s	42.137us	1	1	100.00
		uart_tl_intg_err	1.100s	495.807us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.100s	495.807us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.990s	11.431ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.70744882001492091293201652446833415380419354847056525437659680007357773263673
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 24888847109 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 25510167869 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 25,                                 clk_pulses: 0
        UVM_ERROR @ 25510220501 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 25510273133 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (138 [0x8a] vs 254 [0xfe]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 25510325765 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty