CHIP Simulation Results

Tuesday September 30 2025 19:18:44 UTC

GitHub Revision: `bd069a0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.571m	2.425ms	1	1	100.00
		chip_sw_example_rom	1.191m	1.870ms	1	1	100.00
		chip_sw_example_manufacturer	1.449m	2.521ms	1	1	100.00
		chip_sw_example_concurrency	2.000m	2.521ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.597m	5.154ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.704m	4.315ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.312m	6.642ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.162h	34.585ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.437m	5.528ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.162h	34.585ms	1	1	100.00
		chip_csr_rw	3.704m	4.315ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.690s	161.321us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.980m	3.925ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.980m	3.925ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.980m	3.925ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.121m	4.365ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.121m	4.365ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.769m	4.549ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.157m	3.849ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.173m	4.296ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.731m	3.794ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.083m	8.043ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.544m	4.637ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.637m	4.588ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.637m	4.588ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.585m	3.161ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.463m	2.627ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.204m	3.466ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.232m	2.846ms	1	1	100.00
		chip_tap_straps_testunlock0	6.183m	6.894ms	1	1	100.00
		chip_tap_straps_rma	3.308m	3.632ms	1	1	100.00
		chip_tap_straps_prod	1.599m	3.040ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.647m	2.810ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.252m	9.581ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.167m	4.429ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.167m	4.429ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.428m	8.537ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	23.653m	15.460ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.215m	3.985ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.101m	5.870ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.245m	18.254ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.495m	2.674ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.206m	7.130ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.329m	3.004ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.322m	6.658ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.088m	3.451ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.950m	4.398ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.474m	3.018ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.115m	3.027ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.905m	7.515ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.163m	5.588ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.984m	2.829ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.163m	5.588ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.788m	2.730ms	1	1	100.00
		chip_sw_aes_smoketest	1.958m	3.055ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.293m	3.605ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.989m	2.908ms	1	1	100.00
		chip_sw_csrng_smoketest	2.370m	2.573ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.348m	5.741ms	1	1	100.00
		chip_sw_gpio_smoketest	2.472m	2.886ms	1	1	100.00
		chip_sw_hmac_smoketest	2.723m	2.521ms	1	1	100.00
		chip_sw_kmac_smoketest	2.613m	3.032ms	1	1	100.00
		chip_sw_otbn_smoketest	21.211m	9.706ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.913m	5.742ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.710m	5.547ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.383m	3.040ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.354m	3.032ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.071m	3.055ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.105m	2.982ms	1	1	100.00
		chip_sw_uart_smoketest	2.302m	3.234ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.966m	3.045ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.582m	4.021ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.110h	61.181ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.801m	15.442ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.164m	4.578ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.233m	3.619ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.780m	3.300ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.884h	54.956ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.044h	57.711ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	45.830s	1.961ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	45.830s	1.961ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.162h	34.585ms	1	1	100.00
		chip_same_csr_outstanding	44.259m	29.640ms	1	1	100.00
		chip_csr_hw_reset	2.597m	5.154ms	1	1	100.00
		chip_csr_rw	3.704m	4.315ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.162h	34.585ms	1	1	100.00
		chip_same_csr_outstanding	44.259m	29.640ms	1	1	100.00
		chip_csr_hw_reset	2.597m	5.154ms	1	1	100.00
		chip_csr_rw	3.704m	4.315ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	10.960s	131.142us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.500s	44.800us	1	1	100.00
		xbar_smoke_large_delays	58.240s	9.342ms	1	1	100.00
		xbar_smoke_slow_rsp	53.020s	6.269ms	1	1	100.00
		xbar_random_zero_delays	29.420s	485.127us	1	1	100.00
		xbar_random_large_delays	3.293m	33.599ms	1	1	100.00
		xbar_random_slow_rsp	4.168m	30.871ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	6.340s	62.202us	1	1	100.00
		xbar_error_and_unmapped_addr	14.260s	515.266us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	33.980s	1.745ms	1	1	100.00
		xbar_error_and_unmapped_addr	14.260s	515.266us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.654m	4.256ms	1	1	100.00
		xbar_access_same_device_slow_rsp	9.236m	61.154ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	33.500s	1.410ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.330s	6.314us	1	1	100.00
		xbar_stress_all_with_error	2.055m	2.678ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.681m	4.859ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.248m	300.822us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.801m	15.442ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	38.704m	30.208ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.831m	15.385ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.153m	13.199ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.279m	16.812ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.037m	15.836ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.943m	15.583ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	43.903m	14.975ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.720s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.860s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.170s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.390s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	21.790s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	23.950s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.100s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	20.680s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.120s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.930s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.820s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.030s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.310s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.990s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	23.440s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.130s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.660s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.430s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.500s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.330s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.630s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	22.010s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.870s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	19.590s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.990s	10.140us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.288m	11.780ms	1	1	100.00
		rom_e2e_asm_init_dev	42.229m	18.473ms	1	1	100.00
		rom_e2e_asm_init_prod	42.634m	16.175ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.511m	16.048ms	1	1	100.00
		rom_e2e_asm_init_rma	39.282m	15.207ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.789m	15.655ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	41.308m	16.802ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	42.183m	18.091ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.561m	15.629ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.047m	35.159ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.047m	35.159ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.126m	2.505ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.495m	2.674ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.864m	3.199ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.009m	2.980ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.662m	9.135ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.528m	3.287ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.056m	5.574ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.060m	5.265ms	1	1	100.00
		chip_plic_all_irqs_10	4.313m	3.645ms	1	1	100.00
		chip_plic_all_irqs_20	5.903m	4.318ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.359m	2.842ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.863m	14.330ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.196m	4.751ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.025m	2.568ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.560m	7.803ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.081m	8.664ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.007m	7.409ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.066h	254.525ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.471m	3.900ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.913m	5.742ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.471m	3.900ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.839m	8.291ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.839m	8.291ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.722m	7.167ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.188m	6.098ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.240m	5.463ms	1	1	100.00
		chip_sw_aes_idle	2.009m	2.980ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.136m	3.509ms	1	1	100.00
		chip_sw_kmac_idle	2.486m	2.375ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.320m	5.057ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.429m	3.508ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.778m	4.382ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	6.302m	5.085ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.250m	10.614ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.122m	4.147ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.139m	5.069ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.756m	4.460ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.040m	4.481ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.981m	3.672ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.169m	4.394ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.428m	8.537ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.808m	13.888ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.756m	4.460ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.040m	4.481ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.215m	3.985ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.101m	5.870ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.245m	18.254ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.495m	2.674ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.206m	7.130ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.329m	3.004ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.322m	6.658ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.088m	3.451ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.950m	4.398ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.474m	3.018ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.877m	2.802ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.028m	4.826ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.619m	7.096ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.465m	24.607ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.599m	3.156ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.874m	3.006ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.576m	11.909ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.057m	2.657ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.978m	5.328ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	24.067m	23.610ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.423h	156.943ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.428m	8.537ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.813m	4.743ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.057m	3.878ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.560m	7.803ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.620m	7.473ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.352m	4.860ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.670m	6.409ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.425m	2.604ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.181h	25.862ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.425m	3.116ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.756m	6.924ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.425m	3.116ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.620m	7.473ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.648m	1.990ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	24.061m	21.424ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.308m	5.306ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.101m	5.870ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.562m	3.739ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.215m	3.985ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.024h	42.516ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	24.061m	21.424ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.135m	4.065ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.024h	42.516ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.692m	7.761ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.986m	5.253ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.178m	5.031ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.178m	5.031ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.093m	2.959ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.329m	3.004ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.136m	3.509ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.260m	3.038ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.555m	3.893ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.306m	5.199ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.341m	4.997ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.995m	5.815ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.796m	3.661ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.322m	6.658ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.396m	9.302ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.662m	9.135ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	34.456m	10.419ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.102m	3.070ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.577m	2.800ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.088m	3.451ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.881m	2.906ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	11.350m	5.387ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.486m	2.375ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.056m	5.574ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.232m	2.846ms	1	1	100.00
		chip_tap_straps_rma	3.308m	3.632ms	1	1	100.00
		chip_tap_straps_prod	1.599m	3.040ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.215m	3.080ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.031m	7.201ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.873m	4.196ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.024h	42.516ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.472m	2.993ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.373m	6.331ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.609m	6.944ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.341m	6.810ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.846m	9.134ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.365m	7.521ms	1	1	100.00
		chip_prim_tl_access	2.692m	7.761ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.808m	13.888ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.122m	4.147ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.139m	5.069ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.756m	4.460ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.040m	4.481ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.981m	3.672ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.169m	4.394ms	1	1	100.00
		chip_tap_straps_dev	2.232m	2.846ms	1	1	100.00
		chip_tap_straps_rma	3.308m	3.632ms	1	1	100.00
		chip_tap_straps_prod	1.599m	3.040ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.504m	7.465ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.985m	3.246ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.516m	3.098ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.718m	3.245ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.249m	3.133ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.315m	26.222ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.504m	7.465ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.030h	47.746ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.139h	47.204ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.544m	10.519ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.062h	45.384ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	26.315m	26.222ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.357m	2.376ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	55.680s	2.107ms	1	1	100.00
		rom_volatile_raw_unlock	1.094m	3.054ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	58.009m	17.032ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.245m	18.254ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.240m	5.463ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.240m	5.463ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.240m	5.463ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.356m	3.613ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	24.061m	21.424ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.356m	3.613ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.871m	5.505ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.849m	2.620ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	24.061m	21.424ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.356m	3.613ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.692m	12.294ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.871m	5.505ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.849m	2.620ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.274m	5.452ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.215m	3.080ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.472m	2.993ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.373m	6.331ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.609m	6.944ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.341m	6.810ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.569m	10.113ms	1	1	100.00
		chip_prim_tl_access	2.692m	7.761ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.692m	7.761ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.117m	9.528ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.295m	7.058ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.464m	23.735ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.905m	7.742ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.002m	8.431ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.570m	7.847ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.688m	24.156ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.025m	15.166ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.839m	8.291ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.926m	12.149ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.901m	5.686ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.295m	7.058ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.648m	4.447ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.922m	36.802ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.547m	6.788ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.456m	5.506ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.649m	25.092ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.320m	6.451ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.897m	11.710ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	27.117m	29.102ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.565m	2.622ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.846m	9.134ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.846m	9.134ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.897m	11.710ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.649m	25.092ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.901m	5.686ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.913m	5.742ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.408m	4.031ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.126m	3.464ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.322m	4.085ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.863m	14.330ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.231m	2.413ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.081m	8.664ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.765m	4.175ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.990m	4.194ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.775m	3.036ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.849m	2.620ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.126m	3.464ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.126m	3.464ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.492m	9.136ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	16.570m	13.443ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.408m	4.031ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.160m	3.378ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.532m	6.510ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.308m	3.632ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.504m	7.465ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.060m	5.265ms	1	1	100.00
		chip_plic_all_irqs_10	4.313m	3.645ms	1	1	100.00
		chip_plic_all_irqs_20	5.903m	4.318ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.912m	2.308ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.791m	3.104ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.801m	15.442ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.961m	5.699ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.398m	3.343ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.742m	3.525ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.282m	3.225ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.871m	5.505ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.950m	4.398ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.580m	6.813ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.078m	8.471ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.365m	7.521ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.167m	4.429ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.320m	6.451ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.149m	23.174ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.978m	2.405ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.507m	3.828ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.301m	4.742ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.149m	23.174ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.149m	23.174ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	41.796m	20.316ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	41.796m	20.316ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.316m	5.120ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.047m	35.159ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.312m	2.888ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.752m	3.148ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.251m	3.853ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.563m	3.341ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.202m	8.114ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.404h	32.094ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.266m	11.602ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.201m	3.043ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.722m	2.679ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.887m	2.881ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.670h	72.730ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.034m	3.720ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.450m	14.538ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.419m	11.406ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.002m	12.019ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.661m	4.556ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.295m	5.168ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.283m	4.289ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.288s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.680m	5.428ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.082m	3.171ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.025m	7.484ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.038m	7.850ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.308m	2.251ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.544m	4.720ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.058m	1.848ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.138m	5.306ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.715m	6.740ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.447m	4.121ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.897m	11.710ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.450m	14.538ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.419m	11.406ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.002m	12.019ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.213m	5.121ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.198m	4.614ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.580h	38.248ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.580h	38.248ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.178m	3.392ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.121m	4.365ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	52.810m	18.436ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.958m	3.555ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.910m	5.574ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	37.337m	28.051ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.109m	2.859ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.966m	2.571ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.600m	3.348ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.304s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.710m	3.713ms	1	1	100.00
		TOTAL			282	326	86.50

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.84744052198838574614208956138925338894809093723825916840938117386836107472654
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.96438177243825426791433338595472918945468152286055728188413531136293393818104
    Line 503, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.16411707030470141574474702517519168006170058734242667624641564122372695981535
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.108121229718779611283036657424455654440591434704443840301951821318061440015201
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.49534113015435529869893481810771947972607216367780270889334739671288936269901
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.62120932715752602841935830461300647387264812284128030219720450552402707486141
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.35802407184764486459015298190564502991201920668453620723355707713168375791560
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.79072645713746236231069249204313646566358402395122340595126245488153173554263
    Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.71005213665922887561281150532925816878139618203156677460650949163198577010638
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.72296780527802658537282087581341310298365732346313119229688162297485985145437
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.19601083769962822256620337084042497291214272429836489759817376901989440249836
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.106608330942171143183606459262358932987728201376161222672084819941592450371588
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.103767658819578549553934763075440426880118154295532480418535639487283090291867
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.64712061789986039193630676168875896694153266567633027362965028294510199531708
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.139s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.94069624701366959279105256163147214250501115268043070824652967061801810311666
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.167s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.50634614288683560212846203189835725380645148795935447330761551724026154061082
    Line 575, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.35592869442612616071367700509592412002945175364722097004448676389555541409269
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.59118012010755515683102000095663365923033135197354803731358694978508790170686
    Line 546, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.25334298972059008157570807757190870868205435962992478631868210535947302158231
    Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.83910719784356062992216658755968988816134856260776020063599903136443656990234
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3343.460879 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3343.460879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.86161322168597653787699660500243220523979037938895541695608836395429302362970
    Line 446, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 28051.199974 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 28051.199974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99548) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.63689798840369247716486759499634659090404155789119271448984951808881278027508
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3463.727861 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99548) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3463.727861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.89423789535398256275782141955596534406881831296055781324396429678166239898940
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35158.632336 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35158.632336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.98908181535160475954642824147968852878465773062596695804909253721131265686768
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3287.452325 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3287.452325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.90274984145322990751785095916409557885876591056898031796629893874756026210789
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2567.618528 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2567.618528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.11341170113373151742821737127452501819150803510508816612622548305537133967011
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.92051512873964624359259815234741493136069489436689091802287252795353064001747
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3038.177108 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3038.177108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.109008019372262078209570902239241244249519182143121116571326513806260937980584
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1960.579100 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31960) { a_addr: 'h10674  a_data: 'h369124c3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h186c2  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1960.579100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.60032261824818103002675582411458097807447585412130629284167542293858802605621
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3347.779061 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3347.779061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.46424164717254545329169414600429305227177550810818365300856029036993732203392
    Line 229, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 7464.605940 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105f0 read out mismatch
  UVM_INFO @ 7464.605940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.113633076919302997589616378273222455384632455108952422318751210990582122213252
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3619.200000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3619.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.38259026108930626585693718090365079806932975476588499350882382672342134213139
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3299.735000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3299.735000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.74520692016382105590785012739994066739378873844247147147351136889653838642948
    Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15460.221110 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15460.221110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.27850762798493602676623171298036029870694315711324573387458713375665726992870
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3720.432403 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3720.432403 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.73087616956521596886742970408414945866581632073703708136867509755570324012165
    Line 463, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.69589185291346002989363568926474955467402136951506265574749276903297451535156
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.18396334374858695712475778748322853684895130272897664186141253449343102045203
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 14537.554241 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14537.554241 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217418) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.72830194021699531489386606937688971658670358777442252127484276679125846510768
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5527.842255 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@217418) { a_addr: 'h10774  a_data: 'hcf12475c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h181e4  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5527.842255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---