ADC_CTRL Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.840s	6.093ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.200s	725.434us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.380s	578.347us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	37.720s	27.283ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.330s	1.112ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.250s	581.132us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.380s	578.347us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.112ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.070m	169.495ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.409m	161.075ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.071m	328.581ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	8.061m	503.242ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	7.636m	532.856ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.814m	387.753ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.773m	503.687ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.929m	331.631ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.600s	4.525ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	43.220s	25.485ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	41.540s	104.775ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.271m	163.864ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.590s	532.587us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.210s	382.577us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.530s	691.124us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.530s	691.124us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.200s	725.434us	1	1	100.00
		adc_ctrl_csr_rw	1.380s	578.347us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.112ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.380s	2.889ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.200s	725.434us	1	1	100.00
		adc_ctrl_csr_rw	1.380s	578.347us	1	1	100.00
		adc_ctrl_csr_aliasing	3.330s	1.112ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.380s	2.889ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.920s	7.993ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.670s	8.105ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.670s	8.105ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.410s	47.578ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00