EDN Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.980s	70.690us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.850s	183.642us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.920s	142.833us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.640s	1.034ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.280s	65.925us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.320s	97.899us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	142.833us	1	1	100.00
		edn_csr_aliasing	1.280s	65.925us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.250s	39.668us	1	1	100.00
V2	csrng_commands	edn_genbits	1.250s	39.668us	1	1	100.00
V2	genbits	edn_genbits	1.250s	39.668us	1	1	100.00
V2	interrupts	edn_intr	0.750s	128.921us	1	1	100.00
V2	alerts	edn_alert	0.990s	73.037us	1	1	100.00
V2	errs	edn_err	0.800s	23.692us	1	1	100.00
V2	disable	edn_disable	0.830s	38.014us	1	1	100.00
		edn_disable_auto_req_mode	0.910s	101.658us	1	1	100.00
V2	stress_all	edn_stress_all	6.040s	457.889us	1	1	100.00
V2	intr_test	edn_intr_test	0.840s	14.980us	1	1	100.00
V2	alert_test	edn_alert_test	1.050s	34.662us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.240s	154.427us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.240s	154.427us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.850s	183.642us	1	1	100.00
		edn_csr_rw	0.920s	142.833us	1	1	100.00
		edn_csr_aliasing	1.280s	65.925us	1	1	100.00
		edn_same_csr_outstanding	1.110s	70.990us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.850s	183.642us	1	1	100.00
		edn_csr_rw	0.920s	142.833us	1	1	100.00
		edn_csr_aliasing	1.280s	65.925us	1	1	100.00
		edn_same_csr_outstanding	1.110s	70.990us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.840s	528.972us	1	1	100.00
		edn_tl_intg_err	2.310s	112.697us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.870s	16.933us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.990s	73.037us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.840s	528.972us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.840s	528.972us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.840s	528.972us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.840s	528.972us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.990s	73.037us	1	1	100.00
		edn_sec_cm	3.840s	528.972us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.990s	73.037us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.310s	112.697us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.328m	7.595ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00