I2C Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.500s	10.073ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.770s	1.736ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.890s	321.009us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.850s	16.010us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.890s	8.583ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.480s	86.655us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.110s	25.988us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.850s	16.010us	1	1	100.00
		i2c_csr_aliasing	1.480s	86.655us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.670s	64.802us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	5.502m	58.458ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.278m	13.055ms	1	1	100.00
V2	host_override	i2c_host_override	0.960s	16.625us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.754m	5.048ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	57.320s	9.166ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.380s	948.837us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.760s	553.935us	1	1	100.00
		i2c_host_fifo_reset_rx	3.920s	310.019us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.858m	11.222ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.610s	1.619ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.790s	5.368us	0	1	0.00
V2	target_glitch	i2c_target_glitch	4.200s	2.779ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.405m	58.059ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.900s	1.197ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	19.430s	598.307us	1	1	100.00
		i2c_target_intr_smoke	4.630s	5.071ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.480s	247.420us	1	1	100.00
		i2c_target_fifo_reset_tx	1.340s	345.769us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.684m	28.707ms	1	1	100.00
		i2c_target_stress_rd	19.430s	598.307us	1	1	100.00
		i2c_target_intr_stress_wr	22.610s	9.669ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.100s	5.244ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	59.680s	1.782ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.850s	1.023ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.210s	211.054us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.890s	995.466us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.290s	522.032us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.278m	13.055ms	1	1	100.00
		i2c_host_perf_precise	1.890s	311.901us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	5.610s	1.619ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.570s	439.178us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.500s	1.988ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.460s	2.218ms	1	1	100.00
		i2c_target_nack_txstretch	1.230s	171.458us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.780s	305.873us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.070s	3.125ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	44.473us	1	1	100.00
V2	intr_test	i2c_intr_test	0.710s	18.311us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.410s	357.060us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.410s	357.060us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.890s	321.009us	1	1	100.00
		i2c_csr_rw	0.850s	16.010us	1	1	100.00
		i2c_csr_aliasing	1.480s	86.655us	1	1	100.00
		i2c_same_csr_outstanding	1.270s	80.975us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.890s	321.009us	1	1	100.00
		i2c_csr_rw	0.850s	16.010us	1	1	100.00
		i2c_csr_aliasing	1.480s	86.655us	1	1	100.00
		i2c_same_csr_outstanding	1.270s	80.975us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	2.140s	268.826us	1	1	100.00
		i2c_sec_cm	0.820s	150.829us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.140s	268.826us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.510s	926.875us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.250s	318.543us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	1.160s	32.017us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.13013654535545486007928991499037066167488707428827061573178827979077477592663
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  64802156 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  64802156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.92305850981867776444234070031513518021310093054859160561437418629656627970049
      Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  32017353 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  32017353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.28109660429534756654902198410740809948034949650779418791894249380290822020775
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @   5367583 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @   5367583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.68824734587048011937145114495768334109098315724985326249250680327767511704586
      Line 122, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 58457733554 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @4420939
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.56789640631644699484739007511287196431928951656320095770918757569802805353268
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2779178374 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2779178374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.74278613724978850982572465121346575045996364807166338975108335986931643438133
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 318543116 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 87 [0x57])
        UVM_INFO @ 318543116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.27874216487768553337958038902243723309569734607210766523180170327786929501630
      Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 926875157 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 926875157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.104973521993209869602768936296481139725564529429182907248246015611724090131212
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 171457867 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 171457867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---