KEYMGR Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.050s	103.811us	1	1	100.00
V1	random	keymgr_random	3.750s	114.369us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.880s	55.725us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.950s	75.958us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.910s	682.011us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.870s	356.018us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	0.980s	99.991us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.950s	75.958us	1	1	100.00
		keymgr_csr_aliasing	4.870s	356.018us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	18.610s	2.087ms	1	1	100.00
V2	sideload	keymgr_sideload	3.600s	257.944us	1	1	100.00
		keymgr_sideload_kmac	1.970s	130.980us	1	1	100.00
		keymgr_sideload_aes	2.710s	96.970us	1	1	100.00
		keymgr_sideload_otbn	34.220s	1.853ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.600s	57.819us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.020s	231.910us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.530s	123.186us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	13.950s	2.053ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.620s	29.340us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.600s	184.157us	1	1	100.00
V2	stress_all	keymgr_stress_all	9.730s	1.364ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.740s	43.163us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.780s	71.749us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.170s	26.098us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.170s	26.098us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.880s	55.725us	1	1	100.00
		keymgr_csr_rw	0.950s	75.958us	1	1	100.00
		keymgr_csr_aliasing	4.870s	356.018us	1	1	100.00
		keymgr_same_csr_outstanding	1.790s	98.960us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.880s	55.725us	1	1	100.00
		keymgr_csr_rw	0.950s	75.958us	1	1	100.00
		keymgr_csr_aliasing	4.870s	356.018us	1	1	100.00
		keymgr_same_csr_outstanding	1.790s	98.960us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
		keymgr_tl_intg_err	4.570s	1.069ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.360s	169.455us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.360s	169.455us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.360s	169.455us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.360s	169.455us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.690s	255.840us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.570s	1.069ms	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.360s	169.455us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	18.610s	2.087ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.750s	114.369us	1	1	100.00
		keymgr_csr_rw	0.950s	75.958us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.750s	114.369us	1	1	100.00
		keymgr_csr_rw	0.950s	75.958us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.750s	114.369us	1	1	100.00
		keymgr_csr_rw	0.950s	75.958us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.020s	231.910us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.620s	29.340us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.620s	29.340us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.750s	114.369us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.610s	51.181us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.350s	127.073us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.020s	231.910us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.350s	127.073us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.350s	127.073us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.350s	127.073us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.300s	1.754ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.350s	127.073us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.580s	138.322us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.67581613388353769042775863103631720170790612653458637375371213235311047610463
      Line 242, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 138322139 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 138322139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---