PATTGEN Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000s	97.930us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	38.162us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	45.612us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	64.236us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	90.449us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	14.401us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	45.612us	1	1	100.00
		pattgen_csr_aliasing	2.000s	90.449us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	13.783m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	34.000s	1.377ms	1	1	100.00
V2	error	pattgen_error	2.000s	45.707us	1	1	100.00
V2	stress_all	pattgen_stress_all	13.000s	23.441ms	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	53.575us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	18.023us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	262.987us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	262.987us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	38.162us	1	1	100.00
		pattgen_csr_rw	1.000s	45.612us	1	1	100.00
		pattgen_csr_aliasing	2.000s	90.449us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	16.899us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	38.162us	1	1	100.00
		pattgen_csr_rw	1.000s	45.612us	1	1	100.00
		pattgen_csr_aliasing	2.000s	90.449us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	16.899us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	54.956us	1	1	100.00
		pattgen_sec_cm	1.000s	72.808us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	54.956us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	20.000s	1.162ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	67.880us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.79042159412243099244328615861864188509342602363927997443327802429317140460455
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.50585883628906877993858262703373188606927198886159925843108272436941693384358
      Line 221, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1047263810 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1047271974 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1047271974 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 4/5
        UVM_INFO @ 1047302277 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]