f8e4a6c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.010s | 235.893us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.720s | 80.882us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 22.239us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.500s | 292.510us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.740s | 44.554us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.650s | 15.293us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 22.239us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.740s | 44.554us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 1.190s | 488.863us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 2.110s | 1.142ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 11.166m | 3.351s | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 11.166m | 3.351s | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 3.860s | 10.662ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.820s | 65.630us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.680s | 14.768us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.060s | 459.942us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.060s | 459.942us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.720s | 80.882us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.630s | 22.239us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 44.554us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 20.239us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.720s | 80.882us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.630s | 22.239us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 44.554us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 20.239us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.830s | 145.453us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.110s | 91.959us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.110s | 91.959us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 2.760s | 1.989ms | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.870s | 182.287us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 10.200s | 6.285ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.64773100961956076984043528817326824432149117326418803569915613666127347210168
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 1989055192 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc809e704) == 0x1
UVM_INFO @ 1989055192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.69831610358837110610022927553429048702632068324629482292311598264650185030924
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 488862703 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x709e7f04) == 0x1
UVM_INFO @ 488862703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.43814757735430640481535688536376263350360837984650439539278898887192404356586
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 182287271 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 182287271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---