SPI_DEVICE/1R1W Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	52.710s	47.288ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.160s	120.649us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.940s	99.500us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.900s	1.870ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.110s	819.138us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.770s	265.903us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.940s	99.500us	1	1	100.00
		spi_device_csr_aliasing	11.110s	819.138us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	37.081us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.550s	162.271us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.830s	22.166us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	1.483us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.700s	3.847us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.640s	130.372us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.640s	130.372us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.810s	520.851us	1	1	100.00
		spi_device_tpm_sts_read	0.820s	37.029us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.480s	6.817ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.590s	1.384ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.550s	8.542ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.550s	8.542ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.540s	2.771ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.540s	2.771ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.540s	2.771ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.540s	2.771ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.540s	2.771ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	13.810s	22.207ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	30.850s	3.878ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	30.850s	3.878ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	30.850s	3.878ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.870s	216.387us	1	1	100.00
		spi_device_read_buffer_direct	3.470s	314.435us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	30.850s	3.878ms	1	1	100.00
		spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	6.570s	2.975ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.590s	204.630us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.590s	204.630us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	52.710s	47.288ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.260s	2.625ms	1	1	100.00
V2	stress_all	spi_device_stress_all	7.295m	387.390ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.930s	15.045us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.860s	14.647us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.550s	63.351us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.550s	63.351us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.160s	120.649us	1	1	100.00
		spi_device_csr_rw	1.940s	99.500us	1	1	100.00
		spi_device_csr_aliasing	11.110s	819.138us	1	1	100.00
		spi_device_same_csr_outstanding	2.980s	175.426us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.160s	120.649us	1	1	100.00
		spi_device_csr_rw	1.940s	99.500us	1	1	100.00
		spi_device_csr_aliasing	11.110s	819.138us	1	1	100.00
		spi_device_same_csr_outstanding	2.980s	175.426us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.100s	179.800us	1	1	100.00
		spi_device_tl_intg_err	6.510s	1.417ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.510s	1.417ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.082m	55.723ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.92786782779036416340710689886896012722628898682277311705253942642306965668513
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1149201 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[42])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1149201 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1149201 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.104737763759991228694728754380595689178714554100251091820437658890323684873143
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1226391 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x947477 [100101000111010001110111] vs 0x0 [0])
        UVM_ERROR @   1315391 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e2fc [11110001011111100] vs 0x0 [0])
        UVM_ERROR @   1397391 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2da6cd [1011011010011011001101] vs 0x0 [0])
        UVM_ERROR @   1489391 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2da6ca [1011011010011011001010] vs 0x0 [0])
        UVM_ERROR @   1555391 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x109eb2 [100001001111010110010] vs 0x0 [0])