SPI_DEVICE/2P Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	43.910s	5.717ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	15.869us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.120s	230.128us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.760s	1.885ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.360s	416.922us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.180s	336.127us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.120s	230.128us	1	1	100.00
		spi_device_csr_aliasing	10.360s	416.922us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	36.750us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.740s	46.806us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.900s	101.908us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.900s	305.967us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	19.557us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.890s	3.601ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.890s	3.601ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.490s	2.008ms	1	1	100.00
		spi_device_tpm_sts_read	0.770s	67.673us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.350s	11.431ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.630s	1.751ms	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.780s	10.483ms	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.780s	10.483ms	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.820s	100.906us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.820s	100.906us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.820s	100.906us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.820s	100.906us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.820s	100.906us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.830s	5.645ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.620s	248.233us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.620s	248.233us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.620s	248.233us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.360s	1.945ms	1	1	100.00
		spi_device_read_buffer_direct	7.050s	774.241us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.620s	248.233us	1	1	100.00
		spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.100s	3.367ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.750s	29.137us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.750s	29.137us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	43.910s	5.717ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.456m	83.563ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.970s	211.548us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.660s	11.147us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.730s	41.866us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.780s	254.094us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.780s	254.094us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	15.869us	1	1	100.00
		spi_device_csr_rw	1.120s	230.128us	1	1	100.00
		spi_device_csr_aliasing	10.360s	416.922us	1	1	100.00
		spi_device_same_csr_outstanding	1.510s	305.633us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	15.869us	1	1	100.00
		spi_device_csr_rw	1.120s	230.128us	1	1	100.00
		spi_device_csr_aliasing	10.360s	416.922us	1	1	100.00
		spi_device_same_csr_outstanding	1.510s	305.633us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.040s	70.033us	1	1	100.00
		spi_device_tl_intg_err	13.330s	1.583ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.330s	1.583ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	0.870s	11.382us	1	1	100.00
		TOTAL			33	33	100.00