SPI_HOST Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	47.000s	1.540ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	23.406us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	199.832us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	55.902us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	65.955us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	75.307us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	199.832us	1	1	100.00
		spi_host_csr_aliasing	1.000s	65.955us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	134.138us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	16.252us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	66.818us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	180.182us	1	1	100.00
		spi_host_error_cmd	1.000s	34.754us	1	1	100.00
		spi_host_event	10.000s	357.182us	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	392.174us	1	1	100.00
V2	speed	spi_host_speed	2.000s	392.174us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	392.174us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	179.891us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	124.209us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	392.174us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	392.174us	1	1	100.00
V2	duplex	spi_host_smoke	47.000s	1.540ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	47.000s	1.540ms	1	1	100.00
V2	stress_all	spi_host_stress_all	14.000s	2.074ms	1	1	100.00
V2	spien	spi_host_spien	19.000s	1.854ms	1	1	100.00
V2	stall	spi_host_status_stall	26.000s	794.586us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	55.056us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	180.182us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	14.291us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	47.215us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	39.296us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	39.296us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	23.406us	1	1	100.00
		spi_host_csr_rw	1.000s	199.832us	1	1	100.00
		spi_host_csr_aliasing	1.000s	65.955us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	29.491us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	23.406us	1	1	100.00
		spi_host_csr_rw	1.000s	199.832us	1	1	100.00
		spi_host_csr_aliasing	1.000s	65.955us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	29.491us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	355.194us	1	1	100.00
		spi_host_sec_cm	1.000s	431.785us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	355.194us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.917m	29.723ms	1	1	100.00
		TOTAL			26	26	100.00