SRAM_CTRL/MAIN Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.180s	7.427ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	32.835us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	44.959us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.160s	29.521us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.070s	32.757us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.420s	1.312ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	44.959us	1	1	100.00
		sram_ctrl_csr_aliasing	1.070s	32.757us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.966m	17.777ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.859m	4.615ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.418m	31.799ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.806m	13.442ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.986m	32.451ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.908m	19.902ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	37.920s	9.633ms	1	1	100.00
V2	executable	sram_ctrl_executable	20.420s	5.902ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.610s	2.025ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.397m	41.334ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.980s	4.680ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.880s	768.570us	1	1	100.00
		sram_ctrl_throughput_w_readback	33.050s	886.239us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.520m	3.882ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.950s	1.402ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	48.699m	87.792ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.970s	11.969us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.520s	274.504us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.520s	274.504us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	32.835us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	44.959us	1	1	100.00
		sram_ctrl_csr_aliasing	1.070s	32.757us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	46.604us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	32.835us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	44.959us	1	1	100.00
		sram_ctrl_csr_aliasing	1.070s	32.757us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	46.604us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	31.750s	7.402ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
		sram_ctrl_tl_intg_err	1.560s	329.936us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.560s	329.936us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.520m	3.882ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.520m	3.882ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	44.959us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.420s	5.902ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.420s	5.902ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.420s	5.902ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	37.920s	9.633ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.240s	693.607us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	31.750s	7.402ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.530s	2.997ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.180s	7.427ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.180s	7.427ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.420s	5.902ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	37.920s	9.633ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.180s	7.427ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.920s	3.208us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.890s	372.370us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.17535339779867334366212037972380029672611401171075198934850390569575093591073
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3208426 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3208426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---