SRAM_CTRL/RET Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.140s	2.740ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	203.970us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	16.557us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.400s	176.962us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.680s	25.083us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.620s	110.584us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	16.557us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	25.083us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.030s	483.817us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.240s	80.913us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	4.360m	11.712ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.214m	3.786ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.800s	362.120us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.442m	1.573ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.530s	310.309us	1	1	100.00
V2	executable	sram_ctrl_executable	2.609m	4.022ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.090s	506.762us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.227m	65.198ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.580s	74.791us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.970s	377.347us	1	1	100.00
		sram_ctrl_throughput_w_readback	9.580s	147.395us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.762m	4.290ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.740s	53.415us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	7.832m	47.865ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.620s	12.156us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.030s	518.410us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.030s	518.410us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	203.970us	1	1	100.00
		sram_ctrl_csr_rw	0.710s	16.557us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	25.083us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	46.004us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	203.970us	1	1	100.00
		sram_ctrl_csr_rw	0.710s	16.557us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	25.083us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	46.004us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.460s	431.490us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
		sram_ctrl_tl_intg_err	1.870s	191.093us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.870s	191.093us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.762m	4.290ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.762m	4.290ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	16.557us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.609m	4.022ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.609m	4.022ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.609m	4.022ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.530s	310.309us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.740s	67.213us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.460s	431.490us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.910s	256.095us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.140s	2.740ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.140s	2.740ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.609m	4.022ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.530s	310.309us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.140s	2.740ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.630s	2.064us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.319m	6.439ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.34632907541729876963169667653816469946679061641890107030407772397595779359389
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2064149 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2064149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.22068889781317586931486864884888922050734936295238525837416410440625126009515
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 110583878 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @ 110583878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---