SYSRST_CTRL Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.270s	2.137ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	5.340s	2.465ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.220s	2.400ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.810s	2.331ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.780s	4.009ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.450s	2.102ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	44.010s	76.250ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.860s	3.177ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.260s	2.083ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.450s	2.102ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.860s	3.177ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.993m	106.408ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	43.960s	25.095ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	5.410s	3.727ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.570s	3.574ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.140s	2.529ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.660s	2.133ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	6.560s	3.225ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.130s	2.617ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	50.710s	2.111s	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.258m	42.339ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	24.740s	459.971ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.360s	2.021ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.680s	2.013ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	2.980s	2.500ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	2.980s	2.500ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.780s	4.009ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.450s	2.102ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.860s	3.177ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	8.960s	5.013ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.780s	4.009ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.450s	2.102ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.860s	3.177ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	8.960s	5.013ms	1	1	100.00
V2		TOTAL			13	15	86.67
V2S	tl_intg_err	sysrst_ctrl_sec_cm	15.320s	22.047ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	10.260s	22.581ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	10.260s	22.581ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	12.170s	6.303ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.34223838713403919140391054124045802597044055514204642105316786990853373300134
      Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2111111085289 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 2111111210288 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 2111111210288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(4) +/-* has 1 failures:

  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_with_pre_cond.65872976662047878602099753186860548324757428968383315430744461930218800548826
      Line 399, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 25094822097 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(4) +/-4
        UVM_ERROR @ 25094822097 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(4) +/-4
        UVM_INFO @ 25094822097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---