UART Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: f8e4a6c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.000s	684.940us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.690s	31.091us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.800s	14.655us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.330s	95.146us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.920s	15.513us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.870s	21.072us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.800s	14.655us	1	1	100.00
		uart_csr_aliasing	0.920s	15.513us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	9.250s	34.436ms	1	1	100.00
V2	parity	uart_smoke	2.000s	684.940us	1	1	100.00
		uart_tx_rx	9.250s	34.436ms	1	1	100.00
V2	parity_error	uart_intr	1.037m	60.465ms	1	1	100.00
		uart_rx_parity_err	18.180s	53.708ms	1	1	100.00
V2	watermark	uart_tx_rx	9.250s	34.436ms	1	1	100.00
		uart_intr	1.037m	60.465ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.500s	59.866ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.068m	274.341ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	52.710s	98.341ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.037m	60.465ms	1	1	100.00
V2	rx_break_err	uart_intr	1.037m	60.465ms	1	1	100.00
V2	rx_timeout	uart_intr	1.037m	60.465ms	1	1	100.00
V2	perf	uart_perf	7.319m	12.772ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.060s	196.211us	1	1	100.00
V2	line_loopback	uart_loopback	1.060s	196.211us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.890s	38.881ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	11.260s	34.729ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.760s	460.284us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	21.300s	3.838ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.957m	59.281ms	1	1	100.00
V2	stress_all	uart_stress_all	1.461m	188.520ms	1	1	100.00
V2	alert_test	uart_alert_test	0.840s	41.885us	1	1	100.00
V2	intr_test	uart_intr_test	0.710s	15.816us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.320s	126.726us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.320s	126.726us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.690s	31.091us	1	1	100.00
		uart_csr_rw	0.800s	14.655us	1	1	100.00
		uart_csr_aliasing	0.920s	15.513us	1	1	100.00
		uart_same_csr_outstanding	0.730s	186.894us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.690s	31.091us	1	1	100.00
		uart_csr_rw	0.800s	14.655us	1	1	100.00
		uart_csr_aliasing	0.920s	15.513us	1	1	100.00
		uart_same_csr_outstanding	0.730s	186.894us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.110s	39.245us	1	1	100.00
		uart_tl_intg_err	1.250s	78.088us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.250s	78.088us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.620s	2.188ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00