CHIP Simulation Results

Wednesday October 01 2025 17:16:06 UTC

GitHub Revision: `f8e4a6c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.878m	2.471ms	1	1	100.00
		chip_sw_example_rom	1.347m	2.686ms	1	1	100.00
		chip_sw_example_manufacturer	1.849m	2.772ms	1	1	100.00
		chip_sw_example_concurrency	2.274m	2.837ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.490m	5.768ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.945m	5.289ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.878m	4.734ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.242h	34.016ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	46.620s	2.174ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.242h	34.016ms	1	1	100.00
		chip_csr_rw	5.945m	5.289ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	7.990s	210.533us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.857m	4.271ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.857m	4.271ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.857m	4.271ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.474m	4.103ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.474m	4.103ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.311m	4.168ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.415m	4.182ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.866m	4.091ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.729m	7.618ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.209m	3.379ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	19.284m	12.937ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.066m	4.519ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.066m	4.519ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.496m	3.078ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.439m	3.739ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.568m	3.127ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.532m	2.951ms	1	1	100.00
		chip_tap_straps_testunlock0	3.202m	4.211ms	1	1	100.00
		chip_tap_straps_rma	5.025m	5.893ms	1	1	100.00
		chip_tap_straps_prod	1.729m	2.714ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.722m	2.984ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.319m	8.914ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.776m	6.031ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.776m	6.031ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.754m	7.587ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	39.063m	23.492ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.997m	4.864ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.594m	5.335ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.559m	18.120ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.018m	3.322ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.535m	7.183ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.142m	3.074ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.885m	6.742ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.234m	2.567ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.387m	5.260ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.980m	2.534ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.288m	3.011ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.358m	4.384ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.027m	5.521ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.856m	2.946ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.027m	5.521ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.285m	3.135ms	1	1	100.00
		chip_sw_aes_smoketest	3.053m	2.345ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.194m	2.609ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.694m	3.099ms	1	1	100.00
		chip_sw_csrng_smoketest	2.605m	2.566ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.031m	5.975ms	1	1	100.00
		chip_sw_gpio_smoketest	3.427m	3.235ms	1	1	100.00
		chip_sw_hmac_smoketest	3.656m	2.810ms	1	1	100.00
		chip_sw_kmac_smoketest	2.683m	2.617ms	1	1	100.00
		chip_sw_otbn_smoketest	19.837m	10.459ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.441m	5.230ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.782m	6.523ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.797m	2.451ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.983m	3.689ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.123m	2.891ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.426m	3.154ms	1	1	100.00
		chip_sw_uart_smoketest	2.766m	3.161ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.813m	3.370ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.412m	5.005ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.198h	61.919ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.721m	15.058ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.598m	5.586ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.742m	3.225ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.317m	3.250ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.891h	53.685ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.110h	56.548ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	44.540s	1.945ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	44.540s	1.945ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.242h	34.016ms	1	1	100.00
		chip_same_csr_outstanding	51.514m	32.962ms	1	1	100.00
		chip_csr_hw_reset	3.490m	5.768ms	1	1	100.00
		chip_csr_rw	5.945m	5.289ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.242h	34.016ms	1	1	100.00
		chip_same_csr_outstanding	51.514m	32.962ms	1	1	100.00
		chip_csr_hw_reset	3.490m	5.768ms	1	1	100.00
		chip_csr_rw	5.945m	5.289ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	37.750s	1.840ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.510s	53.957us	1	1	100.00
		xbar_smoke_large_delays	48.330s	7.757ms	1	1	100.00
		xbar_smoke_slow_rsp	48.270s	5.376ms	1	1	100.00
		xbar_random_zero_delays	30.780s	554.228us	1	1	100.00
		xbar_random_large_delays	1.992m	20.772ms	1	1	100.00
		xbar_random_slow_rsp	3.769m	28.716ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.790s	292.523us	1	1	100.00
		xbar_error_and_unmapped_addr	7.030s	188.822us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	43.650s	2.112ms	1	1	100.00
		xbar_error_and_unmapped_addr	7.030s	188.822us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.087m	2.744ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.388m	9.495ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.570s	472.435us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.044m	14.750ms	1	1	100.00
		xbar_stress_all_with_error	7.070s	171.529us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.173m	628.168us	1	1	100.00
		xbar_stress_all_with_reset_error	1.059m	404.731us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.721m	15.058ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.324m	26.394ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.426m	15.325ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.983m	13.220ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.897m	15.427ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.229m	16.370ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	44.459m	15.926ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.923m	15.081ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.520s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.130s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.580s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.810s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.420s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.000s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.570s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.500s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.650s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.420s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.310s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.750s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.020s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.420s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.010s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.540s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.350s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.560s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.620s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.610s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.670s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.030s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.070s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.400s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.210s	10.300us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	34.028m	10.883ms	1	1	100.00
		rom_e2e_asm_init_dev	41.901m	16.649ms	1	1	100.00
		rom_e2e_asm_init_prod	43.631m	15.664ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.297m	15.317ms	1	1	100.00
		rom_e2e_asm_init_rma	42.017m	15.481ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.391m	15.314ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.101m	15.684ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.248m	14.567ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.763m	16.171ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.948m	34.920ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.948m	34.920ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.276m	3.479ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.018m	3.322ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.655m	3.063ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.184m	3.034ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.869m	8.262ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.743m	3.246ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.191m	5.241ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.950m	5.592ms	1	1	100.00
		chip_plic_all_irqs_10	3.520m	3.086ms	1	1	100.00
		chip_plic_all_irqs_20	6.267m	4.473ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.692m	3.246ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	18.930m	11.929ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.733m	3.331ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.891m	2.438ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	20.318m	8.137ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.290m	7.938ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.428m	7.961ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.307h	254.440ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.895m	4.057ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.441m	5.230ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.895m	4.057ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.708m	10.348ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.708m	10.348ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.203m	6.828ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	7.403m	5.987ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.658m	5.846ms	1	1	100.00
		chip_sw_aes_idle	2.184m	3.034ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.906m	2.804ms	1	1	100.00
		chip_sw_kmac_idle	2.087m	2.924ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.912m	4.568ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.238m	3.410ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	5.217m	4.819ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.576m	4.632ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.131m	9.654ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.384m	4.093ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.688m	5.453ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.954m	3.691ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.234m	4.909ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.297m	3.811ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.448m	5.222ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.754m	7.587ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.553m	13.808ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.954m	3.691ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.234m	4.909ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.997m	4.864ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.594m	5.335ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.559m	18.120ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.018m	3.322ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.535m	7.183ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.142m	3.074ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.885m	6.742ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.234m	2.567ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.387m	5.260ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.980m	2.534ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.596m	3.608ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.799m	4.600ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.433m	7.430ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.836m	24.344ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.637m	3.141ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.103m	2.867ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	22.300m	13.630ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.176m	3.409ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.692m	5.802ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.721m	25.661ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	49.204m	28.283ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.754m	7.587ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.056m	4.965ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.452m	3.673ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	20.318m	8.137ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.638m	8.072ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.403m	3.607ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.124m	7.297ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.081m	2.410ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	53.101m	18.307ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.002m	3.708ms	1	1	100.00
		chip_sw_edn_entropy_reqs	14.276m	7.425ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.002m	3.708ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.638m	8.072ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.214m	2.275ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.201m	18.365ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.414m	5.882ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.594m	5.335ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.789m	4.522ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.997m	4.864ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.024h	43.027ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.201m	18.365ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.747m	3.512ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.024h	43.027ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.970m	8.813ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.536m	5.224ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.635m	5.659ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.635m	5.659ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.226m	2.858ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.142m	3.074ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.906m	2.804ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.775m	2.832ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.871m	3.784ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.098m	4.933ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.796m	5.204ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.756m	5.002ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.981m	3.925ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.885m	6.742ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	18.186m	9.164ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.869m	8.262ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	33.672m	10.450ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.897m	3.410ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.097m	2.573ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.234m	2.567ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.858m	2.733ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.967m	6.905ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.087m	2.924ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.191m	5.241ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.532m	2.951ms	1	1	100.00
		chip_tap_straps_rma	5.025m	5.893ms	1	1	100.00
		chip_tap_straps_prod	1.729m	2.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.761m	3.471ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.767m	10.797ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.745m	4.634ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.024h	43.027ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.849m	3.380ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.655m	6.253ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	11.283m	8.278ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.721m	6.317ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.339m	8.171ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.869m	6.933ms	1	1	100.00
		chip_prim_tl_access	3.970m	8.813ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.553m	13.808ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.384m	4.093ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.688m	5.453ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.954m	3.691ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.234m	4.909ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.297m	3.811ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.448m	5.222ms	1	1	100.00
		chip_tap_straps_dev	1.532m	2.951ms	1	1	100.00
		chip_tap_straps_rma	5.025m	5.893ms	1	1	100.00
		chip_tap_straps_prod	1.729m	2.714ms	1	1	100.00
		chip_rv_dm_lc_disabled	43.310s	2.070ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.930m	3.707ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.618m	3.407ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.771m	3.014ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	30.546m	27.225ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	27.212m	34.491ms	1	1	100.00
		chip_rv_dm_lc_disabled	43.310s	2.070ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.085h	46.461ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.117h	49.671ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.829m	8.418ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.044h	46.302ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	27.212m	34.491ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	56.760s	2.303ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.252m	3.205ms	1	1	100.00
		rom_volatile_raw_unlock	1.024m	1.965ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.934m	16.868ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.559m	18.120ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.658m	5.846ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.658m	5.846ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.658m	5.846ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.353m	3.687ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.201m	18.365ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.353m	3.687ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.876m	5.383ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.863m	2.943ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.201m	18.365ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.353m	3.687ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.697m	7.352ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.876m	5.383ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.863m	2.943ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.623m	4.992ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.761m	3.471ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.849m	3.380ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.655m	6.253ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	11.283m	8.278ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.721m	6.317ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.200m	6.190ms	1	1	100.00
		chip_prim_tl_access	3.970m	8.813ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.970m	8.813ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.187m	10.077ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.279m	8.016ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.020m	25.230ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.189m	7.397ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.157m	8.956ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.067m	6.476ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.460m	25.024ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.496m	15.712ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.708m	10.348ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.787m	10.681ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.489m	4.338ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.279m	8.016ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.773m	4.022ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	42.630m	46.238ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.566m	6.452ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.393m	4.388ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	17.969m	24.756ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.262m	6.125ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.139m	12.224ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.888m	25.744ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.144m	2.396ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.339m	8.171ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.339m	8.171ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.139m	12.224ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	17.969m	24.756ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.489m	4.338ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.441m	5.230ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.462m	3.450ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.175m	4.726ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.592m	5.013ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	18.930m	11.929ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.244m	2.813ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.290m	7.938ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.940m	4.718ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.073m	4.177ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.416m	2.540ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.863m	2.943ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.175m	4.726ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.175m	4.726ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	24.560m	19.695ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.762m	13.640ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.462m	3.450ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.582m	5.321ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.207m	6.835ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	5.025m	5.893ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	43.310s	2.070ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.950m	5.592ms	1	1	100.00
		chip_plic_all_irqs_10	3.520m	3.086ms	1	1	100.00
		chip_plic_all_irqs_20	6.267m	4.473ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.865m	2.822ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.869m	3.046ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.721m	15.058ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.795m	6.701ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.336m	2.924ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.105m	3.847ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.760m	3.163ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.876m	5.383ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.387m	5.260ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.331m	6.461ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.731m	8.465ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.869m	6.933ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.776m	6.031ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.262m	6.125ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.463m	23.623ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.966m	2.947ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.482m	3.441ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.721m	5.208ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.463m	23.623ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.463m	23.623ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.660m	11.285ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.660m	11.285ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.722m	5.837ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.948m	34.920ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.507m	3.316ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.975m	2.808ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.581m	3.631ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.897m	3.894ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	19.272m	7.746ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.460h	31.411ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.076m	12.252ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.833m	2.814ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.497m	3.038ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.478m	2.909ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.587h	71.888ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.932m	3.841ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.979m	15.037ms	0	1	0.00
		rom_e2e_jtag_debug_dev	21.173m	12.520ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.483m	11.546ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.183m	3.840ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.764m	4.724ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.307m	5.056ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.810s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.540m	5.473ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.758m	2.949ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.858m	5.230ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	21.238m	9.252ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.866m	2.435ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.973m	4.900ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.393m	3.105ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.050m	5.139ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.805m	6.896ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.306m	5.292ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.139m	12.224ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.979m	15.037ms	0	1	0.00
		rom_e2e_jtag_debug_dev	21.173m	12.520ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.483m	11.546ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.993m	4.754ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.459m	5.009ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.514h	38.293ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.514h	38.293ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.529m	3.762ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.474m	4.103ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.361m	18.945ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	3.079m	3.191ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.553m	5.425ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	42.401m	36.860ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.183m	2.722ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.523m	3.622ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.271m	4.074ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.854s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.571m	2.763ms	1	1	100.00
		TOTAL			281	326	86.20

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.52700026001649595905859253415780649352768889087069823756271975699088541239792
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.46480490625217396041666464042279785274468345561761698802289098191451771476017
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.91990675216497048517671365756604894848765310179136728051971667824534636026328
    Line 535, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.98586113416952595696081229921385114945904573775654130929685779092451358768976
    Line 562, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.24320781989486825754467326248912110951942196474942153074976800500430928642910
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.41465003103096735259789162398933448487011032708333166605670455345309336017110
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.102855946805909999730299323810051472170910156911963476708646220050687409252386
    Line 532, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.79554634649761792847234478805941469208683749953613885027995081706110779244601
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.65445672336503531811570913628957872486538516484566874668867226621016893874302
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.96239734709092572058699303720859754108917055262416658902874913635109278443077
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.102333518884719027505332771313552489363982118153035506226327719874105195236347
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.76132377412558544749950760232557928387061635029728326034181578643967667797381
    Line 535, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.8476452112833679342719543239294878446865451360344591986316510084032274334168
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.26254861734122405635768844487598712901073727173406597269590797196546620500750
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.161s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.7229075651253738913110453091980509898420437886862599013048054274127443064570
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.164s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.34873294023891526258234577780334728756101002671086449417094405437678226169993
    Line 579, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.113786847946817754432352337680050839139174617361042679672840229242849785180785
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.96718642132934734230306956779393938432690649479449544832014931427187065045299
    Line 555, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.40566303529702460674020967955734614023199106090524842647407998542068453454793
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.99394633316125340942044032461688797530282018443691986326567292026638514976463
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2923.797927 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2923.797927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.23999288316916685119647049484836733935854852005630398199545241409773531389415
    Line 443, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 36860.318663 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 36860.318663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:820) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.97156227303260708912580764289785014183031540328042552721406193686548459310019
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27225.217891 us: (chip_sw_base_vseq.sv:820) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27225.217891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87540) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.32782938394274749741914689311431453690019026680098862139501139378766604294077
Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4726.164160 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87540) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4726.164160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.73557137688320156775045431285846401122796106765846385976730609965300321190866
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11285.261850 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11285.261850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.51070708115355134274428313322768103708241066245894728650026765752645725393344
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34919.599775 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34919.599775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.69666517729719342569316226383752488341919416678064419432911342920052384891865
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3246.355925 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3246.355925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.107987371887761511371153171511505813659077290708957343768969472315140701709173
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2437.642100 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2437.642100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.5219639527154786425631155886427752884318760697398823990187402455983144247474
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.51217610911484087364216465341337361768173788075117820727278243684866528051265
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2832.012270 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2832.012270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40762) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.5568587504628788396312594412068512335858253118633282386030836344491827368575
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1944.672632 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40762) { a_addr: 'h107bc  a_data: 'hc047a551  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h18d3f  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1944.672632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.27141938066963223607234760323353411006613832692193856875534980302610789780287
    Line 199, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 2069.833066 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106cc read out mismatch
  UVM_INFO @ 2069.833066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.68088311083992250865134237691899662707007763318505736191000929484835633792408
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2909.477642 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2909.477642 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.97486919107054441276703641379266463317929654768244165229561816927153078496764
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3225.076000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3225.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.25027732364044583510136806954910874030416100810533901874372176464826044609503
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3249.916000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3249.916000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.109206161159951437081393793121191782238192124208374755349574458869076035155061
    Line 445, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3840.782273 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3840.782273 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.46399580561662238129920818168723764373922020760244949220439915360971514408374
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.93712241363864901985901490889230681269551597183204512684691980456323856369257
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.83569391571530457161555606214115914929309334655049759426634149711460068081866
    Line 449, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 15037.014475 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 15037.014475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34074) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.96484838416769438915886650741837369617101656914615207146489403629805178719431
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2173.695480 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34074) { a_addr: 'h1079c  a_data: 'h66eb0015  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h195ba  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2173.695480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---