ADC_CTRL Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.940s	5.919ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.110s	1.283ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.140s	379.403us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	8.880s	26.921ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.910s	755.345us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.430s	407.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.140s	379.403us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	755.345us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	9.290m	321.545ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.714m	333.409ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	13.364m	494.822ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.012m	169.949ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	15.388m	595.153ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.701m	220.681ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.511m	318.186ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	27.420s	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	1.340s	3.937ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.208m	46.095ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.164m	75.312ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.924m	299.244ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.040s	460.914us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.380s	495.862us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.350s	536.156us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.350s	536.156us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.110s	1.283ms	1	1	100.00
		adc_ctrl_csr_rw	1.140s	379.403us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	755.345us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.170s	2.330ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.110s	1.283ms	1	1	100.00
		adc_ctrl_csr_rw	1.140s	379.403us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	755.345us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.170s	2.330ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.810s	7.705ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.020s	9.079ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.020s	9.079ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.710s	12.843ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.84153427236375464419369764574892324080090017952113800252989862289794975197453
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---