AES/UNMASKED Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: `dbeac2b`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	1.000s	59.435us	1	1	100.00
V1	smoke	aes_smoke	2.000s	131.403us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	104.176us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	86.801us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	526.009us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	121.713us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	101.712us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	86.801us	1	1	100.00
		aes_csr_aliasing	3.000s	121.713us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	131.403us	1	1	100.00
		aes_config_error	2.000s	90.351us	1	1	100.00
		aes_stress	3.000s	240.883us	1	1	100.00
V2	key_length	aes_smoke	2.000s	131.403us	1	1	100.00
		aes_config_error	2.000s	90.351us	1	1	100.00
		aes_stress	3.000s	240.883us	1	1	100.00
V2	back2back	aes_stress	3.000s	240.883us	1	1	100.00
		aes_b2b	4.000s	105.008us	1	1	100.00
V2	backpressure	aes_stress	3.000s	240.883us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	131.403us	1	1	100.00
		aes_config_error	2.000s	90.351us	1	1	100.00
		aes_stress	3.000s	240.883us	1	1	100.00
		aes_alert_reset	2.000s	229.609us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	63.720us	1	1	100.00
		aes_config_error	2.000s	90.351us	1	1	100.00
		aes_alert_reset	2.000s	229.609us	1	1	100.00
V2	trigger_clear_test	aes_clear	2.000s	120.587us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	182.870us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	229.609us	1	1	100.00
V2	stress	aes_stress	3.000s	240.883us	1	1	100.00
V2	sideload	aes_stress	3.000s	240.883us	1	1	100.00
		aes_sideload	2.000s	86.597us	1	1	100.00
V2	deinitialization	aes_deinit	2.000s	85.166us	1	1	100.00
V2	stress_all	aes_stress_all	11.000s	997.820us	0	1	0.00
V2	alert_test	aes_alert_test	2.000s	90.718us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	100.524us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	100.524us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	104.176us	1	1	100.00
		aes_csr_rw	1.000s	86.801us	1	1	100.00
		aes_csr_aliasing	3.000s	121.713us	1	1	100.00
		aes_same_csr_outstanding	1.000s	177.918us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	104.176us	1	1	100.00
		aes_csr_rw	1.000s	86.801us	1	1	100.00
		aes_csr_aliasing	3.000s	121.713us	1	1	100.00
		aes_same_csr_outstanding	1.000s	177.918us	1	1	100.00
V2		TOTAL			12	13	92.31
V2S	reseeding	aes_reseed	3.000s	93.140us	1	1	100.00
V2S	fault_inject	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	107.363us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.490ms	1	1	100.00
		aes_tl_intg_err	3.000s	389.442us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	389.442us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	229.609us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	131.403us	1	1	100.00
		aes_stress	3.000s	240.883us	1	1	100.00
		aes_alert_reset	2.000s	229.609us	1	1	100.00
		aes_core_fi	2.000s	64.384us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	110.655us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.000s	212.416us	1	1	100.00
		aes_stress	3.000s	240.883us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	240.883us	1	1	100.00
		aes_sideload	2.000s	86.597us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.000s	212.416us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.000s	212.416us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.000s	212.416us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.000s	212.416us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.000s	212.416us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	240.883us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	240.883us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.000s	127.043us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.000s	127.043us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	71.360us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.000s	127.043us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	229.609us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_ctr_fi	2.000s	51.513us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.000s	127.043us	1	1	100.00
		aes_control_fi	1.000s	67.641us	1	1	100.00
		aes_cipher_fi	2.000s	71.360us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	3.886ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

0.aes_stress_all.29955089839397349096499848443625219005021249560578526799490947221211974334068
Line 68843, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 997819804 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 997778137 PS)
  UVM_ERROR @ 997819804 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 997819804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.62013663004452182436340187686943820982272605691373549082569908478995597343808
    Line 1330, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3886455135 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3886455135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```