CSRNG Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.000s	17.986us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	31.649us	1	1	100.00
V1	csr_rw	csrng_csr_rw	2.000s	35.066us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	6.000s	114.673us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	375.803us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.000s	25.369us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.000s	35.066us	1	1	100.00
		csrng_csr_aliasing	5.000s	375.803us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	5.000s	132.681us	1	1	100.00
V2	alerts	csrng_alert	7.000s	590.270us	1	1	100.00
V2	err	csrng_err	2.000s	6.108us	0	1	0.00
V2	cmds	csrng_cmds	10.000s	300.593us	1	1	100.00
V2	life cycle	csrng_cmds	10.000s	300.593us	1	1	100.00
V2	stress_all	csrng_stress_all	4.683m	7.663ms	1	1	100.00
V2	intr_test	csrng_intr_test	2.000s	41.934us	1	1	100.00
V2	alert_test	csrng_alert_test	2.000s	38.642us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	4.000s	166.008us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	4.000s	166.008us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	31.649us	1	1	100.00
		csrng_csr_rw	2.000s	35.066us	1	1	100.00
		csrng_csr_aliasing	5.000s	375.803us	1	1	100.00
		csrng_same_csr_outstanding	2.000s	80.907us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	31.649us	1	1	100.00
		csrng_csr_rw	2.000s	35.066us	1	1	100.00
		csrng_csr_aliasing	5.000s	375.803us	1	1	100.00
		csrng_same_csr_outstanding	2.000s	80.907us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	3.000s	77.052us	1	1	100.00
		csrng_tl_intg_err	6.000s	431.677us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	2.000s	92.076us	1	1	100.00
		csrng_csr_rw	2.000s	35.066us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	7.000s	590.270us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	4.683m	7.663ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	7.000s	590.270us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	4.683m	7.663ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	7.000s	590.270us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	6.000s	431.677us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
		csrng_sec_cm	3.000s	77.052us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	132.681us	1	1	100.00
		csrng_err	2.000s	6.108us	0	1	0.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.883m	3.030ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 1 failures:
  • Test csrng_err has 1 failures.

    • 0.csrng_err.108194016652750943237130886525443751702718455961720705145751187538459376936780
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log

        UVM_FATAL @   6107846 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   6107846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---