EDN Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.860s 38.809us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.910s 20.189us 1 1 100.00
V1 csr_rw edn_csr_rw 0.860s 15.219us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.300s 62.657us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.980s 17.448us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.930s 19.057us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.860s 15.219us 1 1 100.00
edn_csr_aliasing 0.980s 17.448us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 0.980s 27.806us 1 1 100.00
V2 csrng_commands edn_genbits 0.980s 27.806us 1 1 100.00
V2 genbits edn_genbits 0.980s 27.806us 1 1 100.00
V2 interrupts edn_intr 0.920s 31.492us 1 1 100.00
V2 alerts edn_alert 1.160s 34.122us 1 1 100.00
V2 errs edn_err 0.850s 24.158us 1 1 100.00
V2 disable edn_disable 0.810s 103.506us 1 1 100.00
edn_disable_auto_req_mode 0.860s 21.350us 1 1 100.00
V2 stress_all edn_stress_all 2.420s 450.440us 1 1 100.00
V2 intr_test edn_intr_test 0.810s 13.708us 1 1 100.00
V2 alert_test edn_alert_test 0.920s 19.183us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.470s 82.841us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.470s 82.841us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.910s 20.189us 1 1 100.00
edn_csr_rw 0.860s 15.219us 1 1 100.00
edn_csr_aliasing 0.980s 17.448us 1 1 100.00
edn_same_csr_outstanding 1.220s 110.059us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.910s 20.189us 1 1 100.00
edn_csr_rw 0.860s 15.219us 1 1 100.00
edn_csr_aliasing 0.980s 17.448us 1 1 100.00
edn_same_csr_outstanding 1.220s 110.059us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.590s 489.416us 1 1 100.00
edn_tl_intg_err 2.210s 1.114ms 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.790s 50.669us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.160s 34.122us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.590s 489.416us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.590s 489.416us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.590s 489.416us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.590s 489.416us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.160s 34.122us 1 1 100.00
edn_sec_cm 5.590s 489.416us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.160s 34.122us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.210s 1.114ms 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets