HMAC Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.050s 767.553us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.800s 16.448us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.000s 141.573us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.630s 6.640ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.560s 3.778ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.290s 30.120us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.000s 141.573us 1 1 100.00
hmac_csr_aliasing 4.560s 3.778ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.015m 5.577ms 1 1 100.00
V2 back_pressure hmac_back_pressure 23.020s 2.192ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 10.030s 229.792us 1 1 100.00
hmac_test_sha384_vectors 5.703m 19.225ms 1 1 100.00
hmac_test_sha512_vectors 21.290s 666.224us 1 1 100.00
hmac_test_hmac256_vectors 5.480s 169.655us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 1.002ms 1 1 100.00
hmac_test_hmac512_vectors 12.900s 815.981us 1 1 100.00
V2 burst_wr hmac_burst_wr 14.440s 1.111ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.558m 8.419ms 1 1 100.00
V2 error hmac_error 26.180s 591.030us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.192m 2.344ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.050s 767.553us 1 1 100.00
hmac_long_msg 1.015m 5.577ms 1 1 100.00
hmac_back_pressure 23.020s 2.192ms 1 1 100.00
hmac_datapath_stress 4.558m 8.419ms 1 1 100.00
hmac_burst_wr 14.440s 1.111ms 1 1 100.00
hmac_stress_all 1.189m 56.881ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.050s 767.553us 1 1 100.00
hmac_long_msg 1.015m 5.577ms 1 1 100.00
hmac_back_pressure 23.020s 2.192ms 1 1 100.00
hmac_datapath_stress 4.558m 8.419ms 1 1 100.00
hmac_wipe_secret 1.192m 2.344ms 1 1 100.00
hmac_test_sha256_vectors 10.030s 229.792us 1 1 100.00
hmac_test_sha384_vectors 5.703m 19.225ms 1 1 100.00
hmac_test_sha512_vectors 21.290s 666.224us 1 1 100.00
hmac_test_hmac256_vectors 5.480s 169.655us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 1.002ms 1 1 100.00
hmac_test_hmac512_vectors 12.900s 815.981us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.050s 767.553us 1 1 100.00
hmac_long_msg 1.015m 5.577ms 1 1 100.00
hmac_back_pressure 23.020s 2.192ms 1 1 100.00
hmac_datapath_stress 4.558m 8.419ms 1 1 100.00
hmac_burst_wr 14.440s 1.111ms 1 1 100.00
hmac_error 26.180s 591.030us 1 1 100.00
hmac_wipe_secret 1.192m 2.344ms 1 1 100.00
hmac_test_sha256_vectors 10.030s 229.792us 1 1 100.00
hmac_test_sha384_vectors 5.703m 19.225ms 1 1 100.00
hmac_test_sha512_vectors 21.290s 666.224us 1 1 100.00
hmac_test_hmac256_vectors 5.480s 169.655us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 1.002ms 1 1 100.00
hmac_test_hmac512_vectors 12.900s 815.981us 1 1 100.00
hmac_stress_all 1.189m 56.881ms 1 1 100.00
V2 stress_all hmac_stress_all 1.189m 56.881ms 1 1 100.00
V2 alert_test hmac_alert_test 0.820s 12.196us 1 1 100.00
V2 intr_test hmac_intr_test 0.730s 17.577us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.540s 84.956us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.540s 84.956us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.800s 16.448us 1 1 100.00
hmac_csr_rw 1.000s 141.573us 1 1 100.00
hmac_csr_aliasing 4.560s 3.778ms 1 1 100.00
hmac_same_csr_outstanding 2.130s 252.697us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.800s 16.448us 1 1 100.00
hmac_csr_rw 1.000s 141.573us 1 1 100.00
hmac_csr_aliasing 4.560s 3.778ms 1 1 100.00
hmac_same_csr_outstanding 2.130s 252.697us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.030s 670.030us 1 1 100.00
hmac_tl_intg_err 1.960s 106.097us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.960s 106.097us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.050s 767.553us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.580s 79.454us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.443m 2.274ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.010s 16.978us 1 1 100.00
TOTAL 28 28 100.00