I2C Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.670s	3.232ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.730s	3.680ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	20.448us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.740s	26.625us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.010s	807.297us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.020s	195.268us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.840s	46.046us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.740s	26.625us	1	1	100.00
		i2c_csr_aliasing	1.020s	195.268us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.130s	90.637us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	9.395m	12.820ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.719m	6.456ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	22.691us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.101m	6.863ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.298m	6.113ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.360s	720.172us	1	1	100.00
		i2c_host_fifo_fmt_empty	16.130s	3.306ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.800s	332.392us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.073m	33.663ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.280s	1.463ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.860s	53.251us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.820s	929.305us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	33.150s	12.797ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.030s	1.792ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.700s	244.018us	1	1	100.00
		i2c_target_intr_smoke	8.300s	1.191ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.420s	777.560us	1	1	100.00
		i2c_target_fifo_reset_tx	1.080s	524.500us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.959m	33.583ms	1	1	100.00
		i2c_target_stress_rd	5.700s	244.018us	1	1	100.00
		i2c_target_intr_stress_wr	3.413m	21.468ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.500s	994.125us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	20.950s	2.366ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.300s	4.680ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.870s	199.676us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.250s	109.112us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.270s	75.920us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.719m	6.456ms	1	1	100.00
		i2c_host_perf_precise	7.390s	1.290ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.280s	1.463ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.490s	125.694us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.140s	3.770ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.930s	2.348ms	1	1	100.00
		i2c_target_nack_txstretch	1.520s	592.391us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.640s	914.111us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.630s	489.541us	1	1	100.00
V2	alert_test	i2c_alert_test	0.710s	51.236us	1	1	100.00
V2	intr_test	i2c_intr_test	0.710s	87.438us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.280s	262.325us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.280s	262.325us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	20.448us	1	1	100.00
		i2c_csr_rw	0.740s	26.625us	1	1	100.00
		i2c_csr_aliasing	1.020s	195.268us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	213.730us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	20.448us	1	1	100.00
		i2c_csr_rw	0.740s	26.625us	1	1	100.00
		i2c_csr_aliasing	1.020s	195.268us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	213.730us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.770s	182.672us	1	1	100.00
		i2c_sec_cm	1.120s	242.426us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.770s	182.672us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.360s	4.148ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.000s	184.296us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.160s	345.518us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.69522748144965675147270246324010380144820509598327048868614386801602287774514
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  90637403 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  90637403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.92052819246144580919995043243678147499769471662940292852166454455442002100114
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  53251238 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  53251238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.113933903978981426698511726665738506289051721183395535650868738081624252868442
      Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4148463359 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4148463359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.72381586579673376625484693448181945983426162733088697170772498212529667909915
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 345518374 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 345518374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.80085619963310671167299636860302478513636913746462794601580511480580896347177
      Line 163, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 12819802967 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @7699401
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.820726175383680363718840813505863451924431714886214975146788298528641631289
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 929305390 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 929305390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.75614049149474237251936018731056556635115211133178178333278027388807632244590
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 184295671 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 64 [0x40])
        UVM_INFO @ 184295671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.32199541843411878042955040414806280877736230930981052387739873364620358278293
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 592391360 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 592391360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---