| V1 |
smoke |
kmac_smoke |
19.980s |
592.402us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.840s |
70.042us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.890s |
48.161us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
5.560s |
304.907us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.610s |
836.149us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.300s |
207.578us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.890s |
48.161us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.610s |
836.149us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.690s |
10.716us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.110s |
64.718us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
20.070m |
30.447ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
15.903m |
112.557ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
25.198m |
18.270ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.480s |
1.620ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.430s |
1.671ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
15.010s |
3.662ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.633m |
16.122ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
35.072m |
484.603ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.710s |
52.278us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.300s |
92.315us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.721m |
2.871ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
31.360s |
2.044ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
1.863m |
9.433ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.650m |
16.578ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
5.213m |
33.990ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
10.070s |
2.308ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
2.420s |
49.336us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.360s |
161.076us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.500s |
33.192us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
17.820s |
3.624ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
32.770s |
836.052us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
11.458m |
50.585ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.050s |
29.610us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.260s |
130.959us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.060s |
80.816us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.060s |
80.816us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.840s |
70.042us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.890s |
48.161us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.610s |
836.149us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.370s |
95.774us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.840s |
70.042us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.890s |
48.161us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.610s |
836.149us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.370s |
95.774us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.240s |
46.824us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.240s |
46.824us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.240s |
46.824us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.240s |
46.824us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.940s |
104.493us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.309m |
17.479ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.130s |
241.727us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.130s |
241.727us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
32.770s |
836.052us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
19.980s |
592.402us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.721m |
2.871ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.240s |
46.824us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.309m |
17.479ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.309m |
17.479ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.309m |
17.479ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
19.980s |
592.402us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
32.770s |
836.052us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.309m |
17.479ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
4.831m |
12.951ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
19.980s |
592.402us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
47.300s |
4.451ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |