KMAC/UNMASKED Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.960s	2.591ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.870s	62.213us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.950s	18.646us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.180s	987.301us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.010s	1.803ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.990s	38.746us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.950s	18.646us	1	1	100.00
		kmac_csr_aliasing	7.010s	1.803ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.690s	42.141us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.290s	18.340us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.507m	144.060ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.146m	39.681ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	21.321m	35.840ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.646m	33.749ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.110s	1.202ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.080s	956.166us	1	1	100.00
		kmac_test_vectors_shake_128	2.090m	3.673ms	1	1	100.00
		kmac_test_vectors_shake_256	3.615m	11.569ms	1	1	100.00
		kmac_test_vectors_kmac	2.270s	108.707us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.950s	158.969us	1	1	100.00
V2	sideload	kmac_sideload	2.565m	8.354ms	1	1	100.00
V2	app	kmac_app	1.368m	25.029ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.927m	27.136ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	23.130s	5.468ms	1	1	100.00
V2	error	kmac_error	3.173m	44.488ms	1	1	100.00
V2	key_error	kmac_key_error	9.080s	3.341ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	19.750s	10.164ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	17.310s	326.160us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.150s	1.105ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.450s	341.895us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	8.170s	379.674us	1	1	100.00
V2	stress_all	kmac_stress_all	3.980m	60.131ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.770s	40.374us	1	1	100.00
V2	alert_test	kmac_alert_test	0.880s	17.184us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.480s	194.184us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.480s	194.184us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.870s	62.213us	1	1	100.00
		kmac_csr_rw	0.950s	18.646us	1	1	100.00
		kmac_csr_aliasing	7.010s	1.803ms	1	1	100.00
		kmac_same_csr_outstanding	1.920s	116.494us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.870s	62.213us	1	1	100.00
		kmac_csr_rw	0.950s	18.646us	1	1	100.00
		kmac_csr_aliasing	7.010s	1.803ms	1	1	100.00
		kmac_same_csr_outstanding	1.920s	116.494us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.960s	43.617us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.960s	43.617us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.960s	43.617us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.960s	43.617us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.510s	1.279ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.180s	8.325ms	1	1	100.00
		kmac_tl_intg_err	3.100s	230.352us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.100s	230.352us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	8.170s	379.674us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.960s	2.591ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.565m	8.354ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.960s	43.617us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.180s	8.325ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.180s	8.325ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.180s	8.325ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.960s	2.591ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	8.170s	379.674us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.180s	8.325ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.776m	5.307ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.960s	2.591ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.655m	10.191ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.50446480631371080164536329668184684448538125364353093169680160034384155851653
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10163906212 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4807e000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10163906212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.4570377295831983235872927905695065278643356446088917559630196671811609823005
      Line 379, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10190551905 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10190551905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---