PATTGEN Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	99.491us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	49.058us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	25.756us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	335.763us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	77.527us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	63.320us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	25.756us	1	1	100.00
		pattgen_csr_aliasing	1.000s	77.527us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.117m	23.493ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	17.000s	2.045ms	1	1	100.00
V2	error	pattgen_error	2.000s	117.515us	1	1	100.00
V2	stress_all	pattgen_stress_all	8.383m	48.524ms	1	1	100.00
V2	alert_test	pattgen_alert_test	1.000s	11.883us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	14.710us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	74.138us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	74.138us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	49.058us	1	1	100.00
		pattgen_csr_rw	1.000s	25.756us	1	1	100.00
		pattgen_csr_aliasing	1.000s	77.527us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	19.459us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	49.058us	1	1	100.00
		pattgen_csr_rw	1.000s	25.756us	1	1	100.00
		pattgen_csr_aliasing	1.000s	77.527us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	19.459us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	576.082us	1	1	100.00
		pattgen_sec_cm	1.000s	1.443ms	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	576.082us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	44.000s	2.219ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	135.667us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.33412986538926117006038727104336997168384319793820808012608395597199349609664
      Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 262373461 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 262379194 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 262379194 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 262480204 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]