ROM_CTRL/32KB Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.200s 240.672us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.870s 1.006ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.340s 129.692us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.120s 129.754us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.130s 300.513us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.950s 126.527us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.340s 129.692us 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 300.513us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.580s 401.436us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.990s 1.029ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.790s 3.899ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.690s 749.708us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.600s 1.598ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.290s 371.324us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.560s 172.738us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.560s 172.738us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.870s 1.006ms 1 1 100.00
rom_ctrl_csr_rw 5.340s 129.692us 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 300.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 220.116us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.870s 1.006ms 1 1 100.00
rom_ctrl_csr_rw 5.340s 129.692us 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 300.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 220.116us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.360s 4.160ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
rom_ctrl_tl_intg_err 24.600s 533.492us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.200s 240.672us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.200s 240.672us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.200s 240.672us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 24.600s 533.492us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.600s 1.598ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 56.950s 2.360ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.360s 4.160ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.683m 436.160us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.775m 20.681ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00