RV_TIMER Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.760s	111.825us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.820s	38.947us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	12.980us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.830s	294.165us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	20.144us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.760s	17.867us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	12.980us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	20.144us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.780s	65.736us	1	1	100.00
V2	disabled	rv_timer_disabled	1.400s	2.931ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	27.850s	74.676ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	27.850s	74.676ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.530s	2.520ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.520s	44.337us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.710s	35.320us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.890s	597.747us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.890s	597.747us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.820s	38.947us	1	1	100.00
		rv_timer_csr_rw	0.620s	12.980us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	20.144us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	71.031us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.820s	38.947us	1	1	100.00
		rv_timer_csr_rw	0.620s	12.980us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	20.144us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	71.031us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.070s	993.240us	1	1	100.00
		rv_timer_tl_intg_err	0.940s	850.763us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.940s	850.763us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.940s	123.009us	0	1	0.00
V3	max_value	rv_timer_max	0.690s	384.413us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	48.710s	5.813ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			17	19	89.47

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.100329147704282238907385604126355686383628983263612973479845712476099969129851
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 123009403 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xafc13b04) == 0x1
        UVM_INFO @ 123009403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.68810299822654734907349680993340243931156322106136614318611722165467568202662
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 384413091 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 384413091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---