SPI_DEVICE/1R1W Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: `dbeac2b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.930s	5.146ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.050s	26.453us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.960s	135.153us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.940s	1.805ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.760s	1.217ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.590s	52.240us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.960s	135.153us	1	1	100.00
		spi_device_csr_aliasing	5.760s	1.217ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.890s	10.918us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.420s	32.990us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.910s	33.022us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.850s	11.854us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.910s	17.283us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.850s	26.871us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.850s	26.871us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.040s	497.511us	1	1	100.00
		spi_device_tpm_sts_read	0.810s	92.779us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.500s	448.349us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	19.230s	74.175ms	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.720s	4.436ms	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.720s	4.436ms	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.310s	81.546us	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.310s	81.546us	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.310s	81.546us	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.310s	81.546us	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.310s	81.546us	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.250s	1.874ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	32.200s	3.455ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	32.200s	3.455ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	32.200s	3.455ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.140s	1.015ms	1	1	100.00
		spi_device_read_buffer_direct	9.510s	3.238ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	32.200s	3.455ms	1	1	100.00
		spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.734m	83.488ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.890s	245.184us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.890s	245.184us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.930s	5.146ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.960s	4.420ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.220s	452.985us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.640s	120.049us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.050s	18.068us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.790s	52.517us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.790s	52.517us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.050s	26.453us	1	1	100.00
		spi_device_csr_rw	1.960s	135.153us	1	1	100.00
		spi_device_csr_aliasing	5.760s	1.217ms	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	492.421us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.050s	26.453us	1	1	100.00
		spi_device_csr_rw	1.960s	135.153us	1	1	100.00
		spi_device_csr_aliasing	5.760s	1.217ms	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	492.421us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.920s	38.928us	1	1	100.00
		spi_device_tl_intg_err	10.060s	1.184ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.060s	1.184ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds			0	1	0.00
		TOTAL			30	33	90.91

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

Test spi_device_mem_parity has 1 failures.

0.spi_device_mem_parity.14253906211771632223485982737191656198953184524340874849565578370145095423651
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6854047 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[9])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6854047 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6854047 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.74235645621879662182396058009741657107072833822713278938143542122348538505615
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @  14906947 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x368b9 [110110100010111001] vs 0x0 [0])
  UVM_ERROR @  14969947 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf50339 [111101010000001100111001] vs 0x0 [0])
  UVM_ERROR @  15024947 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x74c3a [1110100110000111010] vs 0x0 [0])
  UVM_ERROR @  15093947 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7e656 [1111110011001010110] vs 0x0 [0])
  UVM_ERROR @  15121947 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa542e5 [101001010100001011100101] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 0.spi_device_flash_mode_ignore_cmds.38427198057357317974843574670825526624789647472680318975162387936478158809640
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```