| V1 |
smoke |
spi_device_flash_and_tpm |
1.025m |
7.586ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_device_csr_hw_reset |
1.290s |
154.287us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_device_csr_rw |
1.070s |
19.692us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_device_csr_bit_bash |
8.640s |
1.567ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_device_csr_aliasing |
17.380s |
1.265ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_device_csr_mem_rw_with_rand_reset |
2.560s |
326.047us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_device_csr_rw |
1.070s |
19.692us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
17.380s |
1.265ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_device_mem_walk |
0.780s |
35.303us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_device_mem_partial_access |
1.310s |
56.743us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
csb_read |
spi_device_csb_read |
0.860s |
20.255us |
1 |
1 |
100.00 |
| V2 |
mem_parity |
spi_device_mem_parity |
1.060s |
38.923us |
1 |
1 |
100.00 |
| V2 |
mem_cfg |
spi_device_ram_cfg |
0.740s |
43.014us |
1 |
1 |
100.00 |
| V2 |
tpm_read |
spi_device_tpm_rw |
0.800s |
42.239us |
1 |
1 |
100.00 |
| V2 |
tpm_write |
spi_device_tpm_rw |
0.800s |
42.239us |
1 |
1 |
100.00 |
| V2 |
tpm_hw_reg |
spi_device_tpm_read_hw_reg |
0.860s |
13.786us |
1 |
1 |
100.00 |
|
|
spi_device_tpm_sts_read |
0.800s |
36.388us |
1 |
1 |
100.00 |
| V2 |
tpm_fully_random_case |
spi_device_tpm_all |
23.510s |
6.705ms |
1 |
1 |
100.00 |
| V2 |
pass_cmd_filtering |
spi_device_pass_cmd_filtering |
3.350s |
1.744ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
pass_addr_translation |
spi_device_pass_addr_payload_swap |
1.780s |
91.633us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
pass_payload_translation |
spi_device_pass_addr_payload_swap |
1.780s |
91.633us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_info_slots |
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_status |
spi_device_intercept |
13.760s |
7.646ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_jedec |
spi_device_intercept |
13.760s |
7.646ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_sfdp |
spi_device_intercept |
13.760s |
7.646ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_fast_read |
spi_device_intercept |
13.760s |
7.646ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_pipeline |
spi_device_intercept |
13.760s |
7.646ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
flash_cmd_upload |
spi_device_upload |
2.100s |
132.946us |
1 |
1 |
100.00 |
| V2 |
mailbox_command |
spi_device_mailbox |
8.800s |
512.204us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_outside_command |
spi_device_mailbox |
8.800s |
512.204us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_inside_command |
spi_device_mailbox |
8.800s |
512.204us |
1 |
1 |
100.00 |
| V2 |
cmd_read_buffer |
spi_device_flash_mode |
3.510s |
800.635us |
1 |
1 |
100.00 |
|
|
spi_device_read_buffer_direct |
2.850s |
214.318us |
1 |
1 |
100.00 |
| V2 |
cmd_dummy_cycle |
spi_device_mailbox |
8.800s |
512.204us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
quad_spi |
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
dual_spi |
spi_device_flash_all |
59.440s |
21.942ms |
1 |
1 |
100.00 |
| V2 |
4b_3b_feature |
spi_device_cfg_cmd |
3.840s |
3.399ms |
1 |
1 |
100.00 |
| V2 |
write_enable_disable |
spi_device_cfg_cmd |
3.840s |
3.399ms |
1 |
1 |
100.00 |
| V2 |
TPM_with_flash_or_passthrough_mode |
spi_device_flash_and_tpm |
1.025m |
7.586ms |
1 |
1 |
100.00 |
| V2 |
tpm_and_flash_trans_with_min_inactive_time |
spi_device_flash_and_tpm_min_idle |
2.768m |
103.981ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_device_stress_all |
6.350m |
263.259ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_device_alert_test |
0.860s |
20.804us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_device_intr_test |
0.750s |
31.867us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_device_tl_errors |
2.960s |
269.121us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_device_tl_errors |
2.960s |
269.121us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_device_csr_hw_reset |
1.290s |
154.287us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.070s |
19.692us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
17.380s |
1.265ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
1.350s |
129.235us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_device_csr_hw_reset |
1.290s |
154.287us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.070s |
19.692us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
17.380s |
1.265ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
1.350s |
129.235us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
22 |
22 |
100.00 |
| V2S |
tl_intg_err |
spi_device_sec_cm |
1.290s |
94.452us |
1 |
1 |
100.00 |
|
|
spi_device_tl_intg_err |
9.200s |
725.147us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_device_tl_intg_err |
9.200s |
725.147us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_device_flash_mode_ignore_cmds |
25.540s |
5.610ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
33 |
33 |
100.00 |