SRAM_CTRL/MAIN Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.240s	504.406us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	25.306us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.880s	17.148us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	187.265us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	18.791us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.420s	711.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.880s	17.148us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	18.791us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.093m	21.533ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	59.670s	4.649ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.147m	25.205ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.303m	8.425ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	34.054m	229.873ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.074m	11.065ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	44.000s	9.213ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.393m	43.077ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.690s	3.204ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.906m	12.864ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	34.080s	1.574ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	38.510s	1.439ms	1	1	100.00
		sram_ctrl_throughput_w_readback	44.940s	10.132ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	33.780s	21.314ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.360s	1.469ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.006h	1.507s	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.840s	13.682us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.070s	32.264us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.070s	32.264us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	25.306us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	17.148us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	18.791us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.880s	31.304us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	25.306us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	17.148us	1	1	100.00
		sram_ctrl_csr_aliasing	1.080s	18.791us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.880s	31.304us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.520s	3.861ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
		sram_ctrl_tl_intg_err	3.000s	188.612us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.000s	188.612us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.780s	21.314ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	33.780s	21.314ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.880s	17.148us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.393m	43.077ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.393m	43.077ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.393m	43.077ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	44.000s	9.213ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.160s	4.747ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.520s	3.861ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.710s	1.440ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.240s	504.406us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.240s	504.406us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.393m	43.077ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	44.000s	9.213ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.240s	504.406us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	9.099us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	28.850s	1.408ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.53508305229614312636397820048374324552890518869970651031923843471742872343937
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9099038 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9099038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---