SRAM_CTRL/RET Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	0.860s	101.124us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	28.613us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	59.377us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.470s	138.609us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	12.189us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.510s	146.790us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	59.377us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.189us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.120s	299.518us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.230s	283.174us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.935m	24.902ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.168m	20.716ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	45.290s	3.847ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.960m	14.792ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.690s	414.471us	1	1	100.00
V2	executable	sram_ctrl_executable	3.937m	9.238ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.920s	62.209us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.700m	5.958ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	28.580s	125.871us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	49.420s	174.535us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.730s	56.452us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.861m	7.665ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.770s	86.186us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	20.750m	8.539ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.590s	25.027us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.690s	124.868us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.690s	124.868us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	28.613us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	59.377us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.189us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.630s	31.486us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	28.613us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	59.377us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.189us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.630s	31.486us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.520s	265.993us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
		sram_ctrl_tl_intg_err	1.740s	843.357us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.740s	843.357us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.861m	7.665ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.861m	7.665ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	59.377us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.937m	9.238ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.937m	9.238ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.937m	9.238ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.690s	414.471us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.780s	66.548us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.520s	265.993us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.940s	38.597us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	0.860s	101.124us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	0.860s	101.124us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.937m	9.238ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.690s	414.471us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	0.860s	101.124us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.680s	22.307us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.824m	5.850ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.98880618800642129717019893435744274079613974380667864487229950103775643073826
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  66548182 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  66548182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.8782666160426380717226839673599377624963096953511948483072744509035761607448
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  22307094 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  22307094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---