SYSRST_CTRL Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.870s	2.128ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	4.910s	2.465ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.370s	2.263ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	0.990s	2.599ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	8.670s	4.014ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.570s	2.030ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	13.950s	39.108ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	3.910s	3.296ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.450s	2.044ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.570s	2.030ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.910s	3.296ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	2.156m	127.237ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	51.730s	27.082ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.040s	3.006ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	4.140s	5.240ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.880s	2.522ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	0.860s	2.101ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	1.210s	3.514ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	4.960s	2.609ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.820s	3.453ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	53.780s	31.004ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	19.020s	10.187ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.380s	2.012ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.960s	2.015ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.030s	2.043ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.030s	2.043ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	8.670s	4.014ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.570s	2.030ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.910s	3.296ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	10.900s	5.308ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	8.670s	4.014ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.570s	2.030ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.910s	3.296ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	10.900s	5.308ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	11.330s	22.078ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	12.310s	22.266ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	12.310s	22.266ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	8.330s	7.008ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:40) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.flash_wp_l_in == rdata_flash_wp_l_in (* [*] vs * [*]) has 1 failures:
  • Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.sysrst_ctrl_stress_all_with_rand_reset.51987298656813357923654986617863201665225243974120033181818726173385084463782
      Line 400, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7008021638 ps: (sysrst_ctrl_pin_access_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.flash_wp_l_in == rdata_flash_wp_l_in (1 [0x1] vs 0 [0x0])
        UVM_ERROR @ 7008021638 ps: (sysrst_ctrl_pin_access_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.ac_present == rdata_ac_present (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 7008021638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---