UART Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.870s	943.602us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.570s	32.885us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.600s	49.584us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.890s	917.322us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	16.686us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.760s	25.524us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.600s	49.584us	1	1	100.00
		uart_csr_aliasing	0.750s	16.686us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	5.360s	27.258ms	1	1	100.00
V2	parity	uart_smoke	1.870s	943.602us	1	1	100.00
		uart_tx_rx	5.360s	27.258ms	1	1	100.00
V2	parity_error	uart_intr	9.680s	32.792ms	1	1	100.00
		uart_rx_parity_err	14.320s	29.983ms	1	1	100.00
V2	watermark	uart_tx_rx	5.360s	27.258ms	1	1	100.00
		uart_intr	9.680s	32.792ms	1	1	100.00
V2	fifo_full	uart_fifo_full	9.760s	40.129ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	57.480s	53.660ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.027m	188.466ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.680s	32.792ms	1	1	100.00
V2	rx_break_err	uart_intr	9.680s	32.792ms	1	1	100.00
V2	rx_timeout	uart_intr	9.680s	32.792ms	1	1	100.00
V2	perf	uart_perf	6.350m	10.600ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.250s	1.183ms	1	1	100.00
V2	line_loopback	uart_loopback	2.250s	1.183ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	26.940s	72.638ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.820s	7.124ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.270s	349.840us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.750s	6.531ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.120m	104.429ms	1	1	100.00
V2	stress_all	uart_stress_all	2.707m	221.723ms	1	1	100.00
V2	alert_test	uart_alert_test	0.640s	127.959us	1	1	100.00
V2	intr_test	uart_intr_test	0.550s	14.308us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.980s	23.653us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.980s	23.653us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.570s	32.885us	1	1	100.00
		uart_csr_rw	0.600s	49.584us	1	1	100.00
		uart_csr_aliasing	0.750s	16.686us	1	1	100.00
		uart_same_csr_outstanding	0.690s	21.166us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.570s	32.885us	1	1	100.00
		uart_csr_rw	0.600s	49.584us	1	1	100.00
		uart_csr_aliasing	0.750s	16.686us	1	1	100.00
		uart_same_csr_outstanding	0.690s	21.166us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.180s	101.904us	1	1	100.00
		uart_tl_intg_err	0.890s	160.548us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.890s	160.548us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	27.760s	2.804ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.8298976377153867215246914979219695235453326149964337929359066843118055144919
      Line 86, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 68679550429 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 68679590429 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 68679630429 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (212 [0xd4] vs 247 [0xf7]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 69053630429 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 69053670429 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty