CHIP Simulation Results

Thursday October 02 2025 19:14:51 UTC

GitHub Revision: `dbeac2b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.825m	3.246ms	1	1	100.00
		chip_sw_example_rom	1.326m	2.468ms	1	1	100.00
		chip_sw_example_manufacturer	1.910m	2.602ms	1	1	100.00
		chip_sw_example_concurrency	1.831m	2.532ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.573m	4.397ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.010m	4.259ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	33.149m	30.856ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.037h	26.507ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.198m	3.064ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.037h	26.507ms	1	1	100.00
		chip_csr_rw	3.010m	4.259ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.910s	228.499us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.208m	4.054ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.208m	4.054ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.208m	4.054ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.702m	3.692ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.702m	3.692ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.644m	4.190ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.392m	4.013ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.313m	4.782ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.501m	3.516ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.235m	8.342ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.891m	4.030ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.438m	4.522ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.438m	4.522ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.016m	3.049ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.251m	5.405ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.793m	3.752ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	7.641m	7.613ms	1	1	100.00
		chip_tap_straps_testunlock0	6.834m	6.423ms	1	1	100.00
		chip_tap_straps_rma	1.578m	2.976ms	1	1	100.00
		chip_tap_straps_prod	16.934m	14.358ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.318m	2.682ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.986m	9.159ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.951m	5.346ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.951m	5.346ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.098m	7.478ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	29.618m	18.655ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.202m	4.318ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.544m	5.948ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.117m	18.605ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.381m	2.980ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.461m	5.865ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.905m	2.582ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.845m	11.892ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.150m	2.206ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.741m	4.700ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.523m	2.695ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.278m	2.919ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.791m	5.577ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.269m	5.577ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.409m	2.832ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.269m	5.577ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.306m	2.536ms	1	1	100.00
		chip_sw_aes_smoketest	2.441m	3.242ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.116m	3.139ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.061m	2.754ms	1	1	100.00
		chip_sw_csrng_smoketest	1.734m	1.971ms	1	1	100.00
		chip_sw_entropy_src_smoketest	14.524m	7.704ms	1	1	100.00
		chip_sw_gpio_smoketest	2.687m	3.145ms	1	1	100.00
		chip_sw_hmac_smoketest	2.805m	3.169ms	1	1	100.00
		chip_sw_kmac_smoketest	2.849m	2.695ms	1	1	100.00
		chip_sw_otbn_smoketest	21.897m	10.876ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.375m	6.324ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.291m	6.109ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.455m	2.265ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.595m	2.975ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.469m	3.547ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.081m	3.206ms	1	1	100.00
		chip_sw_uart_smoketest	1.967m	2.505ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.379m	3.014ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.289m	4.364ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.141h	60.950ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.503m	14.833ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.272m	5.825ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.067m	2.792ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.125m	3.100ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.922h	52.919ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.124h	56.995ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	54.190s	2.233ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	54.190s	2.233ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.037h	26.507ms	1	1	100.00
		chip_same_csr_outstanding	17.211m	14.743ms	1	1	100.00
		chip_csr_hw_reset	2.573m	4.397ms	1	1	100.00
		chip_csr_rw	3.010m	4.259ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.037h	26.507ms	1	1	100.00
		chip_same_csr_outstanding	17.211m	14.743ms	1	1	100.00
		chip_csr_hw_reset	2.573m	4.397ms	1	1	100.00
		chip_csr_rw	3.010m	4.259ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	41.810s	2.060ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.990s	50.660us	1	1	100.00
		xbar_smoke_large_delays	1.014m	8.751ms	1	1	100.00
		xbar_smoke_slow_rsp	52.450s	5.499ms	1	1	100.00
		xbar_random_zero_delays	23.250s	441.135us	1	1	100.00
		xbar_random_large_delays	4.326m	43.834ms	1	1	100.00
		xbar_random_slow_rsp	2.379m	16.389ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.290s	262.990us	1	1	100.00
		xbar_error_and_unmapped_addr	14.800s	197.865us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	18.960s	376.605us	1	1	100.00
		xbar_error_and_unmapped_addr	14.800s	197.865us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.021m	2.235ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.008m	52.005ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	47.430s	2.710ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.951m	5.767ms	1	1	100.00
		xbar_stress_all_with_error	1.729m	2.363ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.483m	632.600us	1	1	100.00
		xbar_stress_all_with_reset_error	17.990s	111.479us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.503m	14.833ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	38.377m	30.279ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.810m	18.243ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.760m	12.712ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.273m	17.090ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.189m	15.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.214m	16.001ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.669m	15.169ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.300s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.370s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.890s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.300s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.820s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.490s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.170s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.660s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.810s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.430s	10.120us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.870s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.110s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.500s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.310s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.770s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.430s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.590s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.380s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.430s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.680s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.750s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.050s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.960s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.050s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.410s	10.140us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.813m	10.360ms	1	1	100.00
		rom_e2e_asm_init_dev	42.632m	16.121ms	1	1	100.00
		rom_e2e_asm_init_prod	41.505m	15.459ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.434m	15.846ms	1	1	100.00
		rom_e2e_asm_init_rma	39.653m	14.865ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.366m	16.065ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	39.034m	15.501ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.324m	15.242ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.002m	16.057ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.739m	34.436ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.739m	34.436ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.526m	3.249ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.381m	2.980ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.012m	2.613ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.191m	3.098ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	18.721m	8.747ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.792m	2.662ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.088m	4.915ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.319m	5.705ms	1	1	100.00
		chip_plic_all_irqs_10	4.383m	3.945ms	1	1	100.00
		chip_plic_all_irqs_20	5.539m	4.066ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.785m	3.441ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.325m	14.431ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.645m	5.301ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.834m	2.369ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.937m	7.991ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.338m	8.378ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.584m	8.289ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.422h	254.325ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.874m	4.014ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.375m	6.324ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.874m	4.014ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.330m	9.578ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.330m	9.578ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.481m	6.856ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.939m	5.622ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.337m	6.035ms	1	1	100.00
		chip_sw_aes_idle	2.191m	3.098ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.493m	3.177ms	1	1	100.00
		chip_sw_kmac_idle	1.877m	2.809ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.725m	3.121ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.395m	3.467ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.942m	4.844ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.311m	3.736ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.450m	9.004ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.767m	4.288ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.737m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	3.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.631m	4.577ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.729m	3.860ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.540m	4.849ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.098m	7.478ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.522m	4.631ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	3.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.631m	4.577ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.202m	4.318ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.544m	5.948ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.117m	18.605ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.381m	2.980ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.461m	5.865ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.905m	2.582ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.845m	11.892ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.150m	2.206ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.741m	4.700ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.523m	2.695ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.611m	2.705ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.942m	3.998ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.768m	7.214ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.377m	25.729ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.284m	2.795ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.362m	3.272ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.552m	9.427ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.270m	3.439ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.110m	4.151ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.467m	20.889ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.125h	133.746ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.098m	7.478ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.995m	4.710ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.112m	3.652ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.937m	7.991ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.714m	6.833ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.550m	4.623ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.323m	6.721ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.153m	3.045ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.143h	25.769ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.761m	3.084ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.494m	6.639ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.761m	3.084ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.714m	6.833ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.919m	3.514ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.087m	18.427ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.211m	5.408ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.544m	5.948ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.677m	4.265ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.202m	4.318ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.026h	42.632ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.087m	18.427ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.161m	3.078ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.026h	42.632ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.704m	12.320ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.992m	5.089ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.684m	4.882ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.684m	4.882ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.296m	2.517ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.905m	2.582ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.493m	3.177ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.827m	2.712ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.064m	4.218ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.992m	4.514ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.046m	5.067ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.335m	5.156ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.274m	3.156ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.845m	11.892ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	20.572m	9.536ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	18.721m	8.747ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.054m	12.621ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.240m	3.171ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.772m	2.251ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.150m	2.206ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.078m	2.326ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	24.377m	11.396ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.877m	2.809ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.088m	4.915ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	7.641m	7.613ms	1	1	100.00
		chip_tap_straps_rma	1.578m	2.976ms	1	1	100.00
		chip_tap_straps_prod	16.934m	14.358ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.208m	3.607ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.238m	8.397ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.464m	4.472ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.026h	42.632ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.003m	3.667ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.752m	6.642ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.435m	5.657ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.116m	5.331ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.712m	8.879ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.328m	8.408ms	1	1	100.00
		chip_prim_tl_access	5.704m	12.320ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.522m	4.631ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.767m	4.288ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.737m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	3.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.631m	4.577ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.729m	3.860ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.540m	4.849ms	1	1	100.00
		chip_tap_straps_dev	7.641m	7.613ms	1	1	100.00
		chip_tap_straps_rma	1.578m	2.976ms	1	1	100.00
		chip_tap_straps_prod	16.934m	14.358ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.924m	4.922ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.868m	3.005ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.624m	3.510ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.843m	3.768ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.306m	2.933ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.948m	26.329ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.924m	4.922ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.087h	46.194ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.173h	48.914ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.489m	9.980ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.044h	48.300ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.948m	26.329ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.064m	2.054ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.031m	2.685ms	1	1	100.00
		rom_volatile_raw_unlock	1.067m	2.387ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.031m	16.831ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.117m	18.605ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.337m	6.035ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.337m	6.035ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.337m	6.035ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.409m	3.050ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.087m	18.427ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.409m	3.050ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.660m	4.198ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.719m	2.818ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.087m	18.427ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.409m	3.050ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.680m	11.447ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.660m	4.198ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.719m	2.818ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.786m	5.071ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.208m	3.607ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.003m	3.667ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.752m	6.642ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.435m	5.657ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.116m	5.331ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.921m	5.304ms	1	1	100.00
		chip_prim_tl_access	5.704m	12.320ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.704m	12.320ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.708m	8.560ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.766m	7.275ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.836m	21.579ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.324m	7.633ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.436m	7.763ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.301m	8.033ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.752m	24.127ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.086m	13.630ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.330m	9.578ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.628m	11.984ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.627m	5.293ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.766m	7.275ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.634m	5.668ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.248m	33.342ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.238m	5.853ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.544m	4.512ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.570m	26.792ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.412m	6.600ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.025m	9.901ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.032m	20.517ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.140m	3.218ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.712m	8.879ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.712m	8.879ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.025m	9.901ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	29.570m	26.792ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.627m	5.293ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.375m	6.324ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.995m	3.405ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.242m	4.091ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.106m	3.502ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.325m	14.431ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.538m	2.947ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	19.338m	8.378ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.761m	4.231ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.653m	4.675ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.091m	2.386ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.719m	2.818ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.242m	4.091ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.242m	4.091ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.032m	5.904ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.010m	13.038ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.995m	3.405ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.866m	5.017ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.828m	4.763ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.578m	2.976ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.924m	4.922ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.319m	5.705ms	1	1	100.00
		chip_plic_all_irqs_10	4.383m	3.945ms	1	1	100.00
		chip_plic_all_irqs_20	5.539m	4.066ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.317m	2.807ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.619m	3.100ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.503m	14.833ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.417m	5.534ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.881m	2.826ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.319m	3.898ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.138m	2.787ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.660m	4.198ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.741m	4.700ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.576m	7.358ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.103m	9.094ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.328m	8.408ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.951m	5.346ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.412m	6.600ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.951m	24.067ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.808m	3.195ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.971m	3.668ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.460m	4.296ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.951m	24.067ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.951m	24.067ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.910m	21.079ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.910m	21.079ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.427m	5.626ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.739m	34.436ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.728m	2.881ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.567m	3.283ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.019m	3.745ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.582m	4.266ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.668m	8.246ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.472h	32.007ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.490m	12.024ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.416m	2.708ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.270m	2.788ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.262m	3.050ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.672h	71.432ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.485m	6.102ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.750m	10.052ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.440m	3.185ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.511m	2.696ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.439m	3.769ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.908m	5.488ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.912m	4.757ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.757s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.681m	5.319ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.348m	2.862ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.150m	7.112ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.642m	7.145ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.543m	2.599ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.527m	4.786ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.012m	2.461ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.675m	5.836ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.973m	6.680ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.640m	5.302ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.025m	9.901ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.750m	10.052ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.440m	3.185ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.511m	2.696ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.223m	5.391ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.324m	5.000ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.573h	38.432ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.573h	38.432ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.274m	3.946ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.702m	3.692ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.564m	18.799ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.352m	2.717ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.521m	4.337ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	39.593m	36.527ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.684m	3.253ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.030m	3.065ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.680m	3.754ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.971s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.373m	2.476ms	1	1	100.00
		TOTAL			282	326	86.50

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.7847435783641422931292109799977024846078963828600693210374956057349726239418
    Line 527, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.75047777950080252977156765957454809139573268009471372332392473389150417440130
    Line 536, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.78418199679039356699198602073074439728999267150379525926277919522502334717269
    Line 570, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.66956721615825853227913992118949470936792976555878746753919132269166452498199
    Line 573, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.93570317320848336697183375783864278859332105544848366534471204846744456348972
    Line 538, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.100678471369163082325792582058225753662610012868090894754645390608198285315927
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.113907616153592471237411889176620547758081045816843660722895756493671106174632
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.69486610360723391971039485185478629339721500432107175274984668846999693429161
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.46629339737708537972501769638729940429188103444990251916568526562706853255910
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.21351560937099392361283831527258462172428071618869595441576398439171739614463
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.89369070409613718991509892707027140217527874626483694358462405403837703532722
    Line 618, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.32097482619130117957555838517174078949202283235174578648348401766126539801357
    Line 551, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.114396754449350053549430430692679039505304487594616463421137866940256031762002
    Line 566, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.56301487378898700853863020664238100661493094898048182348619920772766124218556
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.63404262930258916510510320369708923558908441042227209691030474867219389034425
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.152s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.73419822252984256440569625732305528067035146205714080376593812898488882165599
    Line 574, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.79973833250950545594982802787685999697236236362061224007587996462792326895623
    Line 560, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.37938428227061399052733800298852993798037815781791515786351879363689074358292
    Line 579, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.94686333996664315819526422283538558246341147897168044242811990322441112707666
    Line 568, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.101645963196759093566966765118460559507155595602781361976640804459436413350839
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2825.721940 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2825.721940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.95829612363717135285017883656992916178584723906394752179685531464078221073512
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 36527.454935 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 36527.454935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110844) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.34565641389609952885792650222184404173137347178451880835628951708383157567036
Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4091.171898 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110844) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4091.171898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.15513820424971311072827894097023293544722023760826272878541908821927791825264
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34435.553569 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34435.553569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.106965483216959993117118328299541310767958697726996263295781048567035886696773
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2662.035870 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2662.035870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.65631829154021943904617853970857968043354897927988800964362695191613133230933
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2368.757240 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2368.757240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.85466000689377398189953076644930324367642900162335326249093231179271370428419
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.53477836327458243006617798857913776229064852484620748859014484556972749179515
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2712.003940 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2712.003940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32774) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.20322841646184497813700748742463132888254054491729274538151558089220615221346
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2232.704229 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32774) { a_addr: 'h104e0  a_data: 'hf8d705ba  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h19576  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2232.704229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.16854043872446391028667911036502275216519997602224477852259145920044282188041
    Line 218, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 4922.123395 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1063c read out mismatch
  UVM_INFO @ 4922.123395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.86334562666541067196944983825196648590842822410056976758010273006078771316261
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3049.512935 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3049.512935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.49575170230436116036213503160356266138064346283910709027782352631557131506116
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2792.376000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2792.376000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.12018387675874045707726640714991755143960694462441364549649403210634803611633
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3099.502000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3099.502000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.65751894498398750359005632893248785544305351109662626175556680530703974179352
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18654.996570 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18654.996570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.100648744337432714955830837800462849060014447226053518568109968099465799579217
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.45339805784272304244557736854752602496923913449106029177917141400763852290821
    Line 518, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:94) [chip_sw_rom_e2e_jtag_debug_vseq] Check failed (breakpoints.size() == *) has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.8014174180262531123494683798379349308152212303451810432202609882737636875367
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3185.222669 us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:94) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_jtag_debug_vseq] Check failed (breakpoints.size() == 3)
  UVM_INFO @ 3185.222669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.52612853585349025106945380823646558365040252110873867077471739430496721333183
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 2696.059389 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 2696.059389 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32358) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.102521729868989542671209040738579509848650836346161104616541560747448405886355
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 3064.073998 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32358) { a_addr: 'h10430  a_data: 'h593a7145  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1a9c2  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3064.073998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---