ADC_CTRL Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.630s	5.870ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.880s	663.806us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.820s	562.924us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.070m	52.242ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.670s	722.276us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.150s	543.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.820s	562.924us	1	1	100.00
		adc_ctrl_csr_aliasing	1.670s	722.276us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.407m	168.517ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.178m	328.428ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	5.872m	482.100ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.940m	329.583ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.546m	173.720ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.089m	191.978ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.760m	164.323ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	3.357m	159.358ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	1.720s	3.713ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	18.540s	40.688ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.910m	133.069ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	40.560s	217.378ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.570s	358.296us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.260s	373.574us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.150s	415.454us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.150s	415.454us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.880s	663.806us	1	1	100.00
		adc_ctrl_csr_rw	1.820s	562.924us	1	1	100.00
		adc_ctrl_csr_aliasing	1.670s	722.276us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.160s	2.061ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.880s	663.806us	1	1	100.00
		adc_ctrl_csr_rw	1.820s	562.924us	1	1	100.00
		adc_ctrl_csr_aliasing	1.670s	722.276us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.160s	2.061ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.630s	8.334ms	1	1	100.00
		adc_ctrl_tl_intg_err	1.980s	5.045ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	1.980s	5.045ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.160s	2.252ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00