EDN Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.850s 24.056us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.800s 55.760us 1 1 100.00
V1 csr_rw edn_csr_rw 0.810s 15.932us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 1.530s 37.731us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.050s 284.765us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.070s 71.461us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.810s 15.932us 1 1 100.00
edn_csr_aliasing 1.050s 284.765us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.180s 57.165us 1 1 100.00
V2 csrng_commands edn_genbits 1.180s 57.165us 1 1 100.00
V2 genbits edn_genbits 1.180s 57.165us 1 1 100.00
V2 interrupts edn_intr 0.830s 34.729us 1 1 100.00
V2 alerts edn_alert 0.880s 40.828us 1 1 100.00
V2 errs edn_err 0.850s 112.698us 1 1 100.00
V2 disable edn_disable 0.820s 11.444us 1 1 100.00
edn_disable_auto_req_mode 0.910s 118.350us 1 1 100.00
V2 stress_all edn_stress_all 1.160s 225.969us 1 1 100.00
V2 intr_test edn_intr_test 0.780s 20.251us 1 1 100.00
V2 alert_test edn_alert_test 0.830s 31.041us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.890s 286.525us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.890s 286.525us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.800s 55.760us 1 1 100.00
edn_csr_rw 0.810s 15.932us 1 1 100.00
edn_csr_aliasing 1.050s 284.765us 1 1 100.00
edn_same_csr_outstanding 1.120s 137.330us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.800s 55.760us 1 1 100.00
edn_csr_rw 0.810s 15.932us 1 1 100.00
edn_csr_aliasing 1.050s 284.765us 1 1 100.00
edn_same_csr_outstanding 1.120s 137.330us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.230s 552.996us 1 1 100.00
edn_tl_intg_err 3.760s 292.355us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.840s 26.204us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.880s 40.828us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.230s 552.996us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.230s 552.996us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.230s 552.996us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.230s 552.996us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.880s 40.828us 1 1 100.00
edn_sec_cm 6.230s 552.996us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.880s 40.828us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.760s 292.355us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets