I2C Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	41.070s	1.237ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	31.070s	5.407ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.850s	142.483us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.900s	18.110us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.760s	1.387ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.290s	104.884us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.010s	37.238us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.900s	18.110us	1	1	100.00
		i2c_csr_aliasing	1.290s	104.884us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.180s	37.939us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.421m	45.100ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	20.030s	3.541ms	1	1	100.00
V2	host_override	i2c_host_override	0.930s	50.521us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.162m	4.692ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.054m	1.587ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.020s	2.001ms	1	1	100.00
		i2c_host_fifo_fmt_empty	12.280s	1.288ms	1	1	100.00
		i2c_host_fifo_reset_rx	5.560s	436.448us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	41.140s	4.588ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	17.790s	1.100ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.430s	50.961us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.190s	1.807ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.052m	53.394ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.480s	648.978us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	34.230s	1.025ms	1	1	100.00
		i2c_target_intr_smoke	6.490s	951.742us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.240s	154.656us	1	1	100.00
		i2c_target_fifo_reset_tx	0.860s	361.162us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.193m	39.682ms	1	1	100.00
		i2c_target_stress_rd	34.230s	1.025ms	1	1	100.00
		i2c_target_intr_stress_wr	4.810s	3.257ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.200s	5.671ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.660s	5.155ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.060s	1.464ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.760s	1.263ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.360s	873.665us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.070s	183.166us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	20.030s	3.541ms	1	1	100.00
		i2c_host_perf_precise	1.520s	54.469us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	17.790s	1.100ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.970s	280.161us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.780s	1.615ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.110s	1.667ms	1	1	100.00
		i2c_target_nack_txstretch	1.230s	201.882us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	8.210s	758.206us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.820s	558.539us	1	1	100.00
V2	alert_test	i2c_alert_test	0.670s	44.435us	1	1	100.00
V2	intr_test	i2c_intr_test	0.830s	49.697us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.380s	182.952us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.380s	182.952us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.850s	142.483us	1	1	100.00
		i2c_csr_rw	0.900s	18.110us	1	1	100.00
		i2c_csr_aliasing	1.290s	104.884us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	62.633us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.850s	142.483us	1	1	100.00
		i2c_csr_rw	0.900s	18.110us	1	1	100.00
		i2c_csr_aliasing	1.290s	104.884us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	62.633us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.140s	55.602us	1	1	100.00
		i2c_sec_cm	0.790s	47.183us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.140s	55.602us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.870s	1.210ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.940s	104.354us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.050s	647.951us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.115524599459524011168627702960733771427755719273714809986641875927764483254960
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  37938526 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  37938526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.19377276453681768677586224409231349777022143557009661090302315362016973867511
      Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 45100175527 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 45100175527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.2062779298984086608541628655662848805745307134928056832709152442189904887438
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 647951255 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 647951255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.91966534274722342162724046402906109323019250318194653299577315909889605934968
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1807304661 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1807304661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.31759907346289071000242574313256337460127702512597847320519576159472665481898
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 104353548 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
        UVM_INFO @ 104353548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.81416286204321458616021571923266815243593127064817803911434936460900868951307
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1209685859 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1209685859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.83550686535792048899806086615054356859279537724877611772755357056823849582922
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  50960675 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------