| V1 |
smoke |
kmac_smoke |
8.780s |
349.815us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.250s |
37.878us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.350s |
51.057us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
10.790s |
285.623us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
7.340s |
475.644us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.900s |
153.996us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.350s |
51.057us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.340s |
475.644us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.890s |
20.236us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.160s |
104.052us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
6.760m |
20.505ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
18.733m |
58.876ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
31.056m |
91.171ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.453m |
118.698ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.400s |
830.758us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
18.150s |
11.180ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
3.287m |
39.134ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
4.862m |
41.688ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.880s |
263.387us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.860s |
291.959us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
5.775m |
63.063ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.559m |
5.772ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
3.008m |
18.811ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.996m |
6.997ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.964m |
18.799ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
2.070s |
102.999us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
1.070s |
25.521us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
23.170s |
1.602ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.310s |
333.918us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
40.900s |
10.467ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.750s |
526.145us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
12.812m |
30.898ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.180s |
22.566us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.950s |
99.525us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.070s |
43.120us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.070s |
43.120us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.250s |
37.878us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.350s |
51.057us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.340s |
475.644us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.100s |
94.006us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.250s |
37.878us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.350s |
51.057us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.340s |
475.644us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.100s |
94.006us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.290s |
155.368us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.290s |
155.368us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.290s |
155.368us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.290s |
155.368us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
4.140s |
178.060us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.048m |
6.607ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.970s |
628.124us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.970s |
628.124us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.750s |
526.145us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
8.780s |
349.815us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
5.775m |
63.063ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.290s |
155.368us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.048m |
6.607ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.048m |
6.607ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.048m |
6.607ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
8.780s |
349.815us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.750s |
526.145us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.048m |
6.607ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
3.094m |
15.968ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
8.780s |
349.815us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.509m |
4.016ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |