PATTGEN Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	50.042us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	103.773us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	38.938us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	67.944us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	55.642us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	28.022us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	38.938us	1	1	100.00
		pattgen_csr_aliasing	2.000s	55.642us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.117m	47.530ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	15.000s	2.708ms	1	1	100.00
V2	error	pattgen_error	7.000s	183.871us	1	1	100.00
V2	stress_all	pattgen_stress_all	6.000s	133.287us	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	14.515us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	51.091us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	86.620us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	86.620us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	103.773us	1	1	100.00
		pattgen_csr_rw	2.000s	38.938us	1	1	100.00
		pattgen_csr_aliasing	2.000s	55.642us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	16.234us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	103.773us	1	1	100.00
		pattgen_csr_rw	2.000s	38.938us	1	1	100.00
		pattgen_csr_aliasing	2.000s	55.642us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	16.234us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	335.188us	1	1	100.00
		pattgen_sec_cm	6.000s	148.691us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	335.188us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	29.000s	13.639ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	7.000s	38.852us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.42174361796982936478004759231818893320294575614198470173740271632644342147292
      Line 121, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3762837052 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 3762857473 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3762857473 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 3763049783 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.890558536010271321915211422895277542679905559740072544985067451032675752556
      Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 133287073 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10182