ROM_CTRL/32KB Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.020s	228.314us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.670s	177.345us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.170s	963.325us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.890s	178.695us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.150s	127.011us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.600s	388.270us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.170s	963.325us	1	1	100.00
		rom_ctrl_csr_aliasing	4.150s	127.011us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.610s	131.708us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.900s	468.170us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.900s	1.174ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	11.210s	338.849us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.690s	1.083ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	5.560s	549.705us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.620s	766.858us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.620s	766.858us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.670s	177.345us	1	1	100.00
		rom_ctrl_csr_rw	3.170s	963.325us	1	1	100.00
		rom_ctrl_csr_aliasing	4.150s	127.011us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.860s	127.892us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.670s	177.345us	1	1	100.00
		rom_ctrl_csr_rw	3.170s	963.325us	1	1	100.00
		rom_ctrl_csr_aliasing	4.150s	127.011us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.860s	127.892us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	17.500s	599.032us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
		rom_ctrl_tl_intg_err	43.160s	974.823us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.020s	228.314us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.020s	228.314us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.020s	228.314us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	43.160s	974.823us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
		rom_ctrl_kmac_err_chk	11.690s	1.083ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	50.810s	1.215ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	17.500s	599.032us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.395m	1.003ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.829m	5.882ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.10344405091424736520944115011700131251790480109107823954612839165277390420193
      Line 178, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 27587240ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 27587240ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 27587240ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))