RV_TIMER Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.970s	36.939us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.740s	42.597us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.700s	23.959us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.900s	63.470us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.620s	37.831us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.740s	55.884us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.700s	23.959us	1	1	100.00
		rv_timer_csr_aliasing	0.620s	37.831us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.090s	1.931ms	0	1	0.00
V2	disabled	rv_timer_disabled	1.210s	2.794ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	6.796m	1.181s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	6.796m	1.181s	1	1	100.00
V2	stress	rv_timer_stress_all	8.080s	5.926ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.610s	25.802us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.540s	11.369us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.090s	60.419us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.090s	60.419us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.740s	42.597us	1	1	100.00
		rv_timer_csr_rw	0.700s	23.959us	1	1	100.00
		rv_timer_csr_aliasing	0.620s	37.831us	1	1	100.00
		rv_timer_same_csr_outstanding	0.840s	86.993us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.740s	42.597us	1	1	100.00
		rv_timer_csr_rw	0.700s	23.959us	1	1	100.00
		rv_timer_csr_aliasing	0.620s	37.831us	1	1	100.00
		rv_timer_same_csr_outstanding	0.840s	86.993us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.990s	68.676us	1	1	100.00
		rv_timer_tl_intg_err	1.150s	378.618us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.150s	378.618us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.740s	207.543us	0	1	0.00
V3	max_value	rv_timer_max	0.600s	44.877us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	48.040s	25.206ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.83778984711973977436297452089610019486162858063906892420680026821699383443315
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 207543449 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6ad96304) == 0x1
        UVM_INFO @ 207543449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.113911512028894009859001381954862842714906863958368475697296448202301403331707
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 1930828910 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xee82af04) == 0x1
        UVM_INFO @ 1930828910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.59466497159676704215535051477643386618258272546382712107337230437572205914890
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  44876828 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  44876828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---