SPI_DEVICE/1R1W Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.957m	70.871ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.130s	24.614us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.270s	158.780us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.910s	3.488ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.860s	1.616ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.740s	261.048us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.270s	158.780us	1	1	100.00
		spi_device_csr_aliasing	10.860s	1.616ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.840s	55.123us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.100s	179.816us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.830s	27.383us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	3.051us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.700s	3.708us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.320s	665.552us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.320s	665.552us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.170s	14.062ms	1	1	100.00
		spi_device_tpm_sts_read	0.870s	11.270us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.090s	2.755ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.280s	4.939ms	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.570s	2.928ms	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.570s	2.928ms	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	1.750s	45.176us	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	1.750s	45.176us	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.750s	45.176us	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	1.750s	45.176us	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.750s	45.176us	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.120s	4.279ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.890s	1.015ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.890s	1.015ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.890s	1.015ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.230s	1.948ms	1	1	100.00
		spi_device_read_buffer_direct	2.930s	746.196us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.890s	1.015ms	1	1	100.00
		spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.010m	170.156ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.000s	68.808us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.000s	68.808us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.957m	70.871ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	42.600s	3.032ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.071m	6.743ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.740s	43.682us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	12.292us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.590s	514.409us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.590s	514.409us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.130s	24.614us	1	1	100.00
		spi_device_csr_rw	1.270s	158.780us	1	1	100.00
		spi_device_csr_aliasing	10.860s	1.616ms	1	1	100.00
		spi_device_same_csr_outstanding	3.270s	818.337us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.130s	24.614us	1	1	100.00
		spi_device_csr_rw	1.270s	158.780us	1	1	100.00
		spi_device_csr_aliasing	10.860s	1.616ms	1	1	100.00
		spi_device_same_csr_outstanding	3.270s	818.337us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.170s	162.343us	1	1	100.00
		spi_device_tl_intg_err	9.620s	2.093ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.620s	2.093ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	41.840s	8.643ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.89833244387843940249279653771946863629491704728627533085401499840670737655282
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2418081 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[47])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2418081 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2418081 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.113468136344758012715009181799317468254438902608335325082667725007888166688047
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1073872 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67fd44 [11001111111110101000100] vs 0x0 [0])
        UVM_ERROR @   1148872 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ebd [11111010111101] vs 0x0 [0])
        UVM_ERROR @   1210872 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe5b95 [111111100101101110010101] vs 0x0 [0])
        UVM_ERROR @   1245872 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3308e9 [1100110000100011101001] vs 0x0 [0])
        UVM_ERROR @   1259872 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaff6ae [101011111111011010101110] vs 0x0 [0])