SPI_DEVICE/2P Simulation Results

Monday October 06 2025 17:11:21 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.173m	54.506ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.910s	130.487us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.260s	34.086us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.140s	2.524ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.520s	5.107ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.070s	94.326us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.260s	34.086us	1	1	100.00
		spi_device_csr_aliasing	16.520s	5.107ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	12.222us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.750s	370.511us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.770s	26.654us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.880s	152.694us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.700s	53.744us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.660s	543.631us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.660s	543.631us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.130s	9.531ms	1	1	100.00
		spi_device_tpm_sts_read	0.730s	115.655us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	32.600s	22.975ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.730s	1.784ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	12.440s	21.888ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	12.440s	21.888ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	26.570s	8.856ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	26.570s	8.856ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.570s	8.856ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	26.570s	8.856ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.570s	8.856ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.050s	789.393us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	22.580s	7.935ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	22.580s	7.935ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	22.580s	7.935ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	15.070s	1.733ms	1	1	100.00
		spi_device_read_buffer_direct	6.190s	1.106ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	22.580s	7.935ms	1	1	100.00
		spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	37.630s	36.711ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.560s	701.779us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.560s	701.779us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.173m	54.506ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.581m	28.257ms	1	1	100.00
V2	stress_all	spi_device_stress_all	11.403m	454.879ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.780s	35.173us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	16.879us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.290s	739.388us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.290s	739.388us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.910s	130.487us	1	1	100.00
		spi_device_csr_rw	1.260s	34.086us	1	1	100.00
		spi_device_csr_aliasing	16.520s	5.107ms	1	1	100.00
		spi_device_same_csr_outstanding	1.450s	59.543us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.910s	130.487us	1	1	100.00
		spi_device_csr_rw	1.260s	34.086us	1	1	100.00
		spi_device_csr_aliasing	16.520s	5.107ms	1	1	100.00
		spi_device_same_csr_outstanding	1.450s	59.543us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.890s	40.045us	1	1	100.00
		spi_device_tl_intg_err	15.470s	13.352ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.470s	13.352ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.332m	38.912ms	1	1	100.00
		TOTAL			33	33	100.00